Usage Notes - Hitachi H8/3664 Hardware Manual

15.4

Usage Notes

• In master mode, if an instruction to generate a start condition is immediately followed by an
instruction to generate a stop condition, neither condition will be output correctly. To output
consecutive start and stop conditions, after issuing the instruction that generates the start
condition, read the relevant ports, check that SCL and SDA are both low, then issue the
instruction that generates the stop condition. Note that SCL may not yet have gone low when
BBSY is cleared to 0.
• Either of the following two conditions will start the next transfer. Pay attention to these
conditions when reading or writing to ICDR.
 Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from
ICDRT to ICDRS)
 Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from
ICDRS to ICDRR)
• Table 15.5 shows the timing of SCL and SDA output in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
2
Table 15.5 I C Bus Timing (SCL and SDA Output)
Item
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
SDA output bus free time
Start condition output hold time
Retransmission start condition output
setup time
Stop condition output setup time
Data output setup time (master)
Data output setup time (slave)
Data output hold time
336
Symbol Output Timing
t 28t to 256t
SCLO cyc
t 0.5t
SCLHO SCLO
t 0.5t
SCLLO SCLO
t 0.5t
BUFO SCLO
t 0.5t
STAHO SCLO
t 1t
STASO SCLO
t 0.5t
STOSO SCLO
t 1t
SDASO SCLLO
1t – 3t
SCLL
t 3t
SDAHO cyc
Unit
ns
cyc
ns
ns
– 1t ns
cyc
– 1t ns
cyc
ns
+ 2t ns
cyc
– 3t ns
cyc
ns
cyc
ns
Notes