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12.1.2
Block Diagrams
Figure 12.1 is a block diagram of timer W.
Internal clock:
ø
ø/2
ø/4
ø/8
External clock: FTCI
Notation:
TMRW: Timer mode register W (8 bits)
TCRW: Timer control register W (8 bits)
TIERW: Timer interrupt enable register W (8 bits)
TSRW:
Timer status register W (8 bits)
TIOR:
Timer I/O control register (8 bits)
TCNT:
Timer counter (16 bits)
GRA:
General register A (input capture/output compare register: 16 bits)
GRB:
General register B (input capture/output compare register: 16 bits)
GRC:
General register C (input capture/output compare register: 16 bits)
GRD:
General register D (input capture/output compare register: 16 bits)
Clock
selector
Comparator
Figure 12.1 Timer W Block Diagram
Control logic
FTIOA
FTIOB
FTIOC
FTIOD
IRRTW
Internal
data bus
193
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