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Bit 7—Counter Clear (CCLR): Selects how TCNT is cleared.
Bit 7: CCLR
0
1
Bits 6 to 4—Clock Select (CKS2 to CKS0): These bits select the TCNT clock source from four
internal clock sources and one external event.
Bit 6: CKS2 Bit 5: CKS1 Bit 4: CKS0 Function
0
0
1
1
0 or 1
Note: * When internal clock φ is selected, the counter operates by the subclock in subactive or
subsleep mode.
Bit 3—Timer Output Level Setting D (TOD): Sets the value output from the FTIOD pin after
reset until the first compare match D (TCNT and GRD matching signal) is generated. After a
compare match is generated, FTIOD outputs the value specified in timer I/O control register 1
(IOD2 to IOD0).
Bit 3: TOD
0
1
Bit 2—Timer Output Level Setting C (TOC): Sets the value output from the FTIOC pin after
reset until the first compare match C (TCNT and GRC matching signal) is generated. After a
compare match is generated, FTIOC outputs the value specified in timer I/O control register 1
(IOC2 to IOC0).
Bit 2: TOC
0
1
198
Description
TCNT is not cleared by GRA compare match
TCNT is cleared by GRA compare match
0
1
0
1
0 or 1
Description
FTIOD is 0
FTIOD is 1
Description
FTIOC is 0
FTIOC is 1
Internal clock: φ*
Internal clock: φ/2
Internal clock: φ/4
Internal clock: φ/8
Rising edges of the external event input (FTCI)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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