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Bits 6 to 0—Reserved: Write 0 when writing.
7.4
Boot Mode
When boot mode is used, the flash memory programming control program must be prepared in the
host beforehand. The SCI3 to be used is set to asynchronous mode. The transmission/receive
format is 8-bit data, 1 stop-bit, and no parity.
When the boot program built into the LSI is activated, the bit rate of SCI3 is set according to the
host bit rate. Next, the programming control program prepared in the host is received via SCI3,
and is serially transmitted to the programming control program area of the on-chip RAM. The old
data in the flash memory is entirely erased, the program branches to the start address of the
programming control program area, and the execution of the programming control program is
started.
When the control branches to the programming control program, SCI3 terminates the
transmission/receive operation (RE and TE of SCR are 0). However, since the bit rate of SCI3
that has been set is retained, SCI3 can be used continuously for transmission/receive of
programming data or verify data. The TxD pin is in the high-level output state (PCR22 = PDR22
= 1). The values of the general-purpose registers of the CPU immediately after the branch to the
programming control program are undefined. In particular, since the stack pointer (SP) is used for
subroutine calls, specify the stack area at the beginning of the programming control program.
The system configuration in boot mode is shown in figure 7.5, and the boot mode execution
procedure is shown in figure 7.6.
Host
Write program reception
Verify data transmission
Figure 7.5 System Configuration in Boot Mode
LSI
Flash memory
RXD
SCI3
TXD
On-chip RAM
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