Hitachi H8/3664 Hardware Manual page 431

Instruction Mnemonic
BSET BSET Rn, @aa:8
BSR BSR d:8
BST BST #xx:3, Rd
BST #xx:3, @Rd
BST #xx:3, @aa:8
BTST BTST #xx:3, Rd
BTST #xx:3, @Rd
BTST #xx:3, @aa:8
BTST Rn, Rd
BTST Rn, @Rd
BTST Rn, @aa:8
BXOR BXOR #xx:3, Rd
BXOR #xx:3, @Rd
BXOR #xx:3, @aa:8 2
CMP CMP. B #xx:8, Rd
CMP. B Rs, Rd
CMP.W Rs, Rd
DAA DAA.B Rd
DAS DAS.B Rd
DEC DEC.B Rd
DIVXU DIVXU.B Rs, Rd
EEPMOV EEPMOV
INC INC.B Rd
JMP JMP @Rn
JMP @aa:16
JMP @@aa:8
JSR JSR @Rn
JSR @aa:16
JSR @@aa:8
LDC LDC #xx:8, CCR
LDC Rs, CCR
MOV MOV.B #xx:8, Rd
MOV.B Rs, Rd
Note: n: Initial value in R4L. The source and destination operands are accessed n + 1 times each.
Instruction Branch
Fetch Addr. Read
I J
2
2
1
2
2
1
2
2
1
2
2
1
2
1
1
1
1
1
1
1
2
1
2
2
2 1
2
2
2 1
1
1
1
1
Stack Byte Data
Operation Access
K L
2
1
2
2
1
1
1
1
1
1
2n+2*
1
1
1
Word Data Internal
Access Operation
M N
12
1
2
2
2
415