Slave Address Register (Sar) - Hitachi H8/3664 Hardware Manual

15.2.2

Slave Address Register (SAR)

Bit 7
SVA6
Initial value 0
Read/Write R/W
SAR is an 8-bit readable/writable register that stores the slave address and selects the
communication format. When the chip is in slave mode (and the addressing format is selected), if
the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device specified by the master device. SAR is assigned to the same
address as ICMR, and can be written and read only when the ICE bit is cleared to 0 in ICCR.
SAR is initialized to H'00 by a reset.
Bits 7 to 1—Slave Address (SVA6 to SVA0): Set a unique address in bits SVA6 to SVA0,
differing from the addresses of other slave devices connected to the I
Bit 0—Format Select (FS): Used together with the FSX bit in SARX to select the communication
format.
The FS bit also specifies whether or not SAR slave address recognition is performed in slave
mode. For details on formats, refer to section 15.3.1, I
SAR SARX
Bit 0: FS Bit 0: FSX
0 0
1
1 0
1
306
6 5
SVA5 SVA4
0 0
R/W R/W
Operating Mode
2
I C bus format
•
SAR and SARX slave addresses recognized
2
I C bus format
•
SAR slave address recognized
•
SARX slave address ignored
2
I C bus format
•
SAR slave address ignored
•
SARX slave address recognized
Synchronous serial format
•
SAR and SARX slave addresses ignored
4 3
SVA3 SVA2
0 0
R/W R/W
2
C Bus Data Format.
2 1
SVA1 SVA0
0 0
R/W R/W
2
C bus.
(Initial value)
0
FS
0
R/W