Table of Contents
Advertisement
Bit 3—Parity Error (PER): Bit 3 indicates that a parity error has occurred during reception with
parity added in asynchronous mode.
Bit 3: PER
0
1
Notes: 1. When bit RE in SCR3 is cleared to 0, bit PER is not affected and retains its previous
state.
2. Receive data in which it a parity error has occurred is still transferred to RDR, but bit
RDRF is not set. Reception cannot be continued with bit PER set to 1. In synchronous
mode, neither transmission nor reception is possible when bit PER is set to 1.
Bit 2—Transmit End (TEND): Bit 2 indicates that bit TDRE is set to 1 when the last bit of a
transmit character is sent.
Bit 2 is a read-only bit and cannot be modified.
Bit 2: TEND
0
1
Description
Reception in progress or completed*
[Clearing condition]
After reading PER = 1, cleared by writing 0 to PER
A parity error has occurred during reception*
[Setting condition]
When the number of 1 bits in the receive data plus parity bit does not match
the parity designated by bit PM in the serial mode register (SMR)
Description
Transmission in progress
[Clearing conditions]
•
After reading TDRE = 1, cleared by writing 0 to TDRE
•
When data is written to TDR by an instruction
Transmission ended
[Setting conditions]
•
When bit TE in SCR3 is cleared to 0
•
When bit TDRE is set to 1 when the last bit of a transmit character is sent
1
2
(Initial value)
(Initial value)
259
Advertisement
Table of Contents
