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Contention between Buffer Register Write and Input Capture in Buffer Operation: If a
capturing signal is generated in the T2 state of a buffer register write cycle, writing to the buffer
register takes priority and input capture (data transfer from GR to the buffer register) is not
performed. Figure 12.39 shows this timing.
φ
Address
Write signal
Input capture
signal
TCNT
GR
Buffer register
Figure 12.39 Contention between Buffer Register Write and Input Capture
234
Buffer register
write cycle
T1
T2
Buffer register
address
M
N
M
X
Y (Buffer register write data)
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