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Bits 6 to 4—Reserved: These bits cannot be modified and are always read as 1.
Bit 3—Input Capture/Compare Match Interrupt Enable D (IMIED): Enables or disables the
IMID interrupt requested by the IMFD flag of TSRW when IMFD is set to 1.
Bit 3: IMIED
0
1
Bit 2—Input Capture/Compare Match Interrupt Enable C (IMIEC): Enables or disables the
IMIC interrupt requested by the IMFC flag of TSRW when IMFC is set to 1.
Bit 2: IMIEC
0
1
Bit 1—Input Capture/Compare Match Interrupt Enable B (IMIEB): Enables or disables the
IMIB interrupt requested by the IMFB flag of TSRW when IMFB is set to 1.
Bit 1: IMIEB
0
1
Bit 0—Input Capture/Compare Match Interrupt Enable A (IMIEA): Enables or disables the
IMIA interrupt requested by the IMFA flag of TSRW when IMFA is set to 1.
Bit 0: IMIEA
0
1
200
Description
IMID interrupt requested by IMFD flag is disabled
IMID interrupt requested by IMFD flag is enabled
Description
IMIC interrupt requested by IMFC flag is disabled
IMIC interrupt requested by IMFC flag is enabled
Description
IMIB interrupt requested by IMFB flag is disabled
IMIB interrupt requested by IMFB flag is enabled
Description
IMIA interrupt requested by IMFA flag is disabled
IMIA interrupt requested by IMFA flag is enabled
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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