Dtc Source Address Register (Sar); Dtc Destination Address Register (Dar); Dtc Transfer Count Register A (Cra) - Hitachi H8S/2338 Series Hardware Manual

Bit 7 Bit 5
CHNE CHNS
0 –
1 0
1 1
Bits 4 to 0—Reserved: These bits have no effect on DTC operation in the H8S/2338 Series,
H8S/2328 Series, and H8S/2318 Series, and should always be written with 0.
6.2.3

DTC Source Address Register (SAR)

Bit : 23
Initial value :
Unde-
fined
R/W : —
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
6.2.4

DTC Destination Address Register (DAR)

Bit : 23
Initial value :
Unde-
fined
R/W : —
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
6.2.5

DTC Transfer Count Register A (CRA)

Bit : 15
Initial value :
Unde-
fined
R/W : —
← CRAH → ← CRAL →
Description
No chain transfer (DTC data transfer end, activation waiting state entered)
DTC chain transfer
Chain transfer only when transfer counter = 0
22 21 20 19
Unde- Unde- Unde- Unde-
fined fined fined fined
— — — —
22 21 20 19
Unde- Unde- Unde- Unde-
fined fined fined fined
— — — —
14 13 12 11
Unde- Unde- Unde- Unde-
fined fined fined fined
— — — —
– – –
– – –
– – –
– – –
– – –
– – –
– – –
– – –
10 9 8 7
Unde- Unde- Unde- Unde-
fined fined fined fined
— — — —
4 3
Unde- Unde-
fined fined
— —
4 3
Unde- Unde-
fined fined
— —
6 5 4 3
Unde- Unde- Unde- Unde-
fined fined fined fined
— — — —
2 1 0
Unde- Unde- Unde-
fined fined fined
— — —
2 1 0
Unde- Unde- Unde-
fined fined fined
— — —
2 1 0
Unde- Unde- Unde-
fined fined fined
— — —
205