Sw Debug Port; Sw Protocol Introduction; Sw Protocol Sequence; Table 219. Packet Request (8-Bits) - ST STM32F101xx Reference Manual

RM0008
31.8

SW debug port

31.8.1

SW protocol introduction

This synchronous serial protocol uses two pins:
●
SWCLK: clock from host to target
●
SWDIO: bidirectional
The protocol allows two banks of registers (DPACC registers and APACC registers) to be
read and written to.
Bits are transferred LSB-first on the wire.
For SWDIO bidirectional management, the line must be pulled-up on the board (100 KΩ
recommended by ARM).
Each time the direction of SWDIO changes in the protocol, a turnaround time is inserted
where the line is not driven by the host nor the target. By default, this turnaround time is one
bit time, however this can be adjusted by configuring the SWCLK frequency.
31.8.2

SW protocol sequence

Each sequence consist of three phases:
1. Packet request (8 bits) transmitted by the host
2. Acknowledge response (3 bits) transmitted by the target
3. Data transfer phase (33 bits) transmitted by the host or the target

Table 219. Packet request (8-bits)

Bit
0
1
2
4:3
5
6
7
Refer to the Cortex-M3 r1p1 TRM for a detailed description of DPACC and APACC registers.
The packet request is always followed by the turnaround time (default 1 bit) where neither
the host nor target drive the line.
Name
Start Must be "1"
0: DP Access
APnDP
1: AP Access
0: Write Request
RnW
1: Read Request
A(3:2) Address field of the DP or AP registers (refer to
Parity Single bit parity of preceding bits
Stop 0
Not driven by the host. Must be read as "1" by the target
Park
because of the pull-up
Doc ID 13902 Rev 12
Debug support (DBG)
Description
Table 218)
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