When Snooping Is Not Allowed - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
ClK
SNPCYC#
MHITM#
SNPBSY#
~~
____
~
__
~
__
~-JI
I
~=~""----I_----'-_--1--_L-..J1
I X I
BGT#
IG~ORED
X
I
CDB39
Figure 5·14. Snoop Executing before BGT# Is Asserted
The two interlock mechanisms described above provide a flexible method of ensuring
overlapped snoop handling.
5.1.2.4.
NOTE
Even when snoops are delayed, address latching is performed through
activation of SNPSTB#. Note that the MBC must not assert SNPSTB# for a
new snoop operation until it has sampled SNPCYC# active for the first snoop
operation (refer to section 5.1.2.4).
WHEN SNOOPING IS NOT ALLOWED
The previous section described the conditions under which snoops would be blocked by the
82496 Cache Controller. There are some cases in which snoops are not blocked by the 82496
Cache Controller, and yet the MBC must not allow snoops to occur. This section describes
these cases.
The 82496 Cache Controller allows the memory bus controller to pipeline snoop operations. A
second snoop request and snoop address can be supplied to the 82496 Cache Controller prior
to the completion of the current snoop operation. Once SNPSTB# has been sampled active, a
new SNPSTB# (for a pipelined snoop) will be ignored by the 82496 Cache Controller until it
has issued SNPCYC# for the original snoop operation. Figure 5-15 shows the window in
which the MBC must not assert an additional SNPSTB# to the 82496 Cache Controller. After
SNPCYC# has been asserted, a new snoop address will be latched by the 82496 Cache
Controller (with SNPSTB#).
I
NOTE
For each snoop mode, the MBC must not request a second snoop operation
between SNPSTB# and SNPCYC#. For strobed snoop mode, the second
falling edge of SNPSTB# must not be until after the falling edge of
SNPCYC#. For clocked snoop mode, the second SNPSTB# sampled by
5-19