Intel 82496 CACHE CONTROLLER User Manual page 259

HARDWARE INTERFACE
If there is no cycle active on the memory bus, the 82496 Cache Controller is able to drive
BLEC# inactive in the CLK after ADS# (of a cache miss cycle). In this case, the 82491 Cache
SRAM MBE# outputs will be active with the CADS# of the memory bus cycle. Refer to
Figure 5-23 (in the BLEC# pin description).
When an ADS# (for a cache miss cycle) has been issued by the CPU, but not yet handled by
the 82496 Cache Controller because the memory bus is busy, the 82496 Cache Controller will
assert BLEC# for one CLK following CNA# or CRDY# assertion. In this case, the 82491
Cache SRAM MBE# outputs will be valid one CLK after the CADS# of the memory bus
cycle. Refer to Figure 5-24 (in the BLEC# pin description).
If a cycle hits in the 82496 Cache Controller tagRAM, then BLEC# will go inactive for one
CLK, latching the CPU byte enables for one CLK. These are unnecessary since the cycle does
not get issued on the memory bus (i.e., no CADS# is generated). Refer to Figure 5-25 (in the
BLEC# pin description).
Relation to Other Signals
Pin Symbol
Relation to Other Signals
CADS# Address and cycle specification signals (Le., APIC#, CCACHE#, CD/C#, CM/IO#,
CPCD, CPWT, CSCYC, CW/R#, CWAY, KLOCK#, MAP, MBT[3:0], MCACHE#,
MCFA, MSET, MTAG, NENE#, PALLC#, RDYSRC, and SMLN#) are valid with
CADS#.
PAR# MBE# shares a pin with PAR#.
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