Dp[7:0] - Intel 82496 CACHE CONTROLLER User Manual

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HARDWARE INTERFACE
5.2.2.46. DP[7:0]
DP[7:0] Data Parity Pins
CPU data bus Even Byte parity.
InpuVOutput between Pentium processor (pins E21, E19, A 19, D18, D08, A09,
COS, H04) and 82491 Cache SRAM CDATA[3:0] pins.
Synchronous to ClK
Signal Description
Refer to the Pentium™ Processor Data Book for a detailed description of this signal.
Relation to Other Signals
Pin Symbol Relation to Other Signals
CDATA[3:0] The Pentium processor Data parity signals are connected to the 82491 Cache
SRAM CDATA[3:0] pins for 82491 Cache SRAMs configured to be data parity
devices. Refer to section 5.1.6.5.
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