5.1.11. 82496 Cache Controller Cycle Progress Requirements; 82496 Cache Controller Input Signal Recognition Requirements; 82496 Cache Controller And 82491 Cache Sram Crdy# Requirements - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
respect to CDTS# (see CDTS# pin description for details).
5.1.11. 82496 Cache Controller Cycle Progress Requirements
1. All 82496 Cache Controller memory bus cycles initiated by CADS# (not SNP ADS#)
require BGT# and CRDY# activation.
2. KWEND# activation represents only the end of the cacheability window, and does not
imply that the bus has been guaranteed to the 82496 Cache Controller (BGT#).
3. SWEND# activation represents only the end of the snooping window, and does not imply
that the bus has been guaranteed to the 82496 Cache Controller (BGT#) or the closure of
the cacheability window (KWEND#).
4. CRDY# activation represents only the end of the current cycle on the memory bus, and
does not imply the closure of the snooping window (SWEND#).
5. In cycles which do not require KWEND# and/or SWEND# activation, those signals may
be kept inactive. When KWEND# and SWEND# are applicable, they must fulfill the
following precedence rule: BGT#
<=
KWEND#
<=
SWEND#.
6. Cycles initiated by SNPADS# require CRDY# but do not require other cycle progress
signals (BGT#, KWEND#, SWEND#).
5.1.12. 82496 Cache Controller Input Signal Recognition
Requirements
1. CNA# is recognized between BGT# and CRDY#. (BGT#
<=
CNA#
<=
CRDY#).
2. CNA# is recognized between CDTS# and CRDY#. (CDTS#
<=
CNA#
<=
CRDY#).
3. Once a signal is recognized, it is a "don't care" until CRDY#.
4. BGT# is only recognized after CADS# and after the CRDY# of the previous (pipelined)
memory bus cycle, but only if neither SNPCYC# nor SNPBSY# and MHITM# are active
(If SNPBSY# is active, BGT# is only blocked in hits to [M] cases - where the bus would
be writing back the modified data).
5.
If
a signal is not recognized it may be held active until it is recognized (Le. a signal is
simply ignored until the recognition window opens).
5.1.13. 82496 Cache Controller and 82491 Cache SRAM CRDV#
Requirements
1. CRDY# must be after CDTS#. (CDTS#
<
CRDY#).
2. CRDY# must be after BGT#. (BGT#
<
CRDY#).
3. Cycles initiated by SNPADS# require CRDY# but do not require other cycle progress
signals (BGT#, KWEND#, SWEND#).
4. CRDY# must be after KWEND# for line fills and write-throughs with potential allocation.
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