Cdts - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.31.
COTS#
CDTS# Cache Data Strobe
Indicates CPU data bus or memory data is available.
Output from 82496 Cache Controller (pin G05)
Synchronous to ClK
Glitch Free
Signal Description
During read cycles, CDTS# indicates that the CPU data bus path is available in the next CLK.
CDTS# indicates the earliest period in which BRDY# may be supplied to the CPU. The first
BRDY# can be issued to the processor 1 CLK after CDTS# is sampled active by the MBC.
During CPU-initiated write cycles, CDTS# indicates that data is available on the memory bus
(the MBC can provide the first MBRDY# in the next CLK).
During write-back and snoop cycles, the 82496 Cache Controller generates CDTS# to indicate
to the MBC that write-back data is valid in the 82491 Cache SRAM write-back buffer (the
MBC can provide the first MBRDY# in the next CLK).
Note that MBRDY# is sampled by the 82491 Cache SRAM with MCLK (not CPU CLK).
It
is
the responsibility of the MBC to ensure that there is one full CPU CLK between CDTS# driven
active and a following MBRDY#.
For processor inquire cycles, CDTS# informs the MBC that the last piece of inquire data is
valid on the CPU bus. .
CDTS# enables independent address strobes (CADS# and SNPADS#) and data strobes. As
soon as addresses are available, the 82496 Cache Controller can use CADS# to indicate to the
MBC that a new cycle has begun. This allows memory bus cycles to begin even before data is
ready to be provided or received.
When Driven
CDTS# is always valid.
CDTS# is asserted with or following CADS# and after SNPADS# assertion for a duration of
oneCLK.
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