Intel 82496 CACHE CONTROLLER User Manual page 273

HARDWARE INTERFACE
5.2.2.91.
MDOE#
MDOE#
Memory Data Output Enable
Three-states/Enables Memory Data Outputs.
Input to 82491 Cache SRAM (pin 20)
Asynchronous
Signal Description
MDOE# is an 82491 Cache SRAM input that causes the 82491 Cache SRAM to drive its
memory bus. outputs (MDATA[7:0]). When MDOE# is inactive, these lines are floated and
may be used as inputs to the 82491 Cache SRAM. MDOE# is not sampled on any CLK and is
a direct connection to the memory output drivers.
When Sampled
Since MDOE# is a direct connection to the 82491 Cache SRAM memory output drivers,
MDOE# must always be driven to a valid level. When MDOE# becomes active, data in the
82491 Cache SRAM memory buffer is driven to the data outputs with some propagation delay
from MDOE# going active. Similarly, there is some float delay from MDOE# going inactive.
MDOE# must be inactive for the 82491 Cache SRAM to read memory bus data.
Relation to Other Signals
Pin Symbol Relation to Other Signals
MDATA[7:0] MDOE# must be inactive for reading data on the memory bus. MDOE# must be
active for write data to be available on the memory bus.
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