Intel 82496 CACHE CONTROLLER User Manual page 311

HARDWARE INTERFACE
5.2.2.121. SEC2#
SEC2# Lines per Sector
Indicates the lines per sector configuration information.
Configuration Output from 82496 Cache Controller (pin N15), Input to 82491
Cache SRAM (pin 38)
Synchronous to CLK
Signal Description
When driven low to the 82491 Cache SRAM, SEC2# indicates that each tag will represent two
82496 Cache Controller/82491 Cache SRAM cache lines in the 82491 Cache SRAM SRAM. If
SEC2# is driven high to the 82491 Cache SRAM, it indicates that each tag will represent only
one cache line in the 82491 Cache SRAM SRAM.
Relation to Other Signals
Pin Symbol Relation to Other Signals
WBA SEC2# shares a pin with WBA.
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I