Drctm - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.47.
DRCTM#
DRCTM# Memory Bus Direct to [M] State
Signals 82496 Cache Controller to place cached line directly into [M] state.
Input to 82496 Cache Controller (pin N02)
Synchronous to ClK
Internal Pull-up
Signal Description
DRCTM# is a memory bus input to the 82496 Cache Controller. When DRCTM# is sampled
active at the end of the snooping window (while SWEND# is active), the 82496 Cache
Controller moves the line being filled directly to the [M] state. Read-Only and Write-Through
cycles will ignore DRCTM# since the only valid tag states are [I] and
[S].
If MRO# is sampled active during KWEND#, or MWB/WT# is sampled Low during
SWEND#, DRCTM# is ignored.
DRCTM# is used in three circumstances:
1. To simplify external state tracking. External tracking devices can only track [M], [S] and
[I] states. The [E] state can not be tracked externally because cache write hits internally
change [E] lines to the [M] state. DRCTM# can be used to eliminate the [E] state from the
MESI protocol.
NOTE
Usage of DRCTM# to avoid [E] states may be in conflict with the SNPCNA
cycle attribute. Snoops with SNPNCA may cause an [E] state transition.
Usage of DRCTM# to avoid [E] states may also be in conflict with the SYNC
operation. SYNC cycles move an [M] state line to [E]. Refer to Tables 3-4
and 3-6.
2. In read for ownership. During write misses with allocation, the MBC may keep write data
in the 82491 Cache SRAM buffer rather than write it to memory. When the allocation is
initiated, due to MFRZ# being sampled active during MEOC# of the write miss cycle, the
read data fills the area surrounding the data from the write in the memory cycle buffer.
Subsequently, the memory cycle buffer contents are written to the 82491 Cache SRAM
array. The cache would normally tag this data in the [E] state because the cache assumes
that the data was written to main memory. Because the data has been modified, DRCTM#
must be asserted to the 82496 Cache Controller.
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