Sign In
Upload
Manuals
Brands
Intel Manuals
Computer Hardware
855PM
Intel 855PM Manuals
Manuals and User Guides for Intel 855PM. We have
1
Intel 855PM manual available for free PDF download: Design Manual
Intel 855PM Design Manual (372 pages)
Chipset Platform for use with Pentium M and Celeron M Processors
Brand:
Intel
| Category:
Computer Hardware
| Size: 7.64 MB
Table of Contents
Table of Contents
3
Introduction
19
Terminology
19
Referenced Documents
21
System Overview
23
TM Mobile Technology Features
23
Figure 1. Basic System Block Diagram
24
Intel Pentium M Processor/Intel Celeron M Processor
25
Architectural Features
25
Packaging/Power
25
Intel 855PM Memory Controller Hub (MCH)
25
Front Side Bus Support
25
Integrated System Memory DRAM Controller
26
Accelerated Graphics Port (AGP) Interface
26
Packaging/Power
26
Intel 82801DBM I/O Controller Hub (ICH4-M)
27
Packaging/Power
27
Intel Pro/Wireless Network Connection
27
Packaging and Power
28
Firmware Hub (FWH)
28
Packaging/Power
28
General Design Considerations
29
Nominal Board Stack-Up
29
Figure 2. Recommended Board Stack-Up Dimensions
30
FSB Design Guidelines
33
FSB Design Recommendations
33
Recommended Stack-Up Routing and Spacing Assumptions
33
Trace Space to Trace - Reference Plane Separation Ratio
33
Trace Space to Trace Width Ratio
34
Recommended Stack-Up Calculated Coupling Model
34
Figure 3. Trace Spacing Vs. Trace to Reference Plane Example
34
Figure 4. Trace Spacing Vs. Trace Width Example
34
Signal Propagation Time to Distance Relationship and Assumptions
35
Figure 5. Recommended Stack-Up Capacitive Coupling Model
35
Common Clock Signals
36
Table 1. FSB Common Clock Signal Internal Layer Routing Guidelines
37
Table 2. FSB Common Clock Signal External Layer Routing Guidelines
38
Figure 6. Common Clock Signals Example - Intel 855PM MCH Escape Routing
39
Figure 7. Common Clock Signals Example - Processor Escape Routing
39
Figure 8. Common Clock Signals Example - Processor to Intel 855PM MCH Layer 6 Routing
40
Source Synchronous Signals
41
Source Synchronous General Routing Guidelines
41
Figure 9. Layer 6 FSB Source Synchronous Signals GND Referencing
42
Figure 10. Layer 3 FSB Source Synchronous Signals GND Referencing
42
Source Synchronous - Data
43
Table 3. FSB Data Source Synchronous Signal Trace Length Mismatch Mapping
43
Source Synchronous - Address
44
Table 4. FSB Source Synchronous Data Signal Routing Guidelines Topology 1
44
Table 5. FSB Source Synchronous Data Signal Routing Guidelines Topology 2
44
Source Synchronous Signals Recommended Layout Example
45
Table 6. FSB Address Source Synchronous Signal Trace Length Mismatch Mapping
45
Table 7. FSB Source Synchronous Address Signal Routing Guidelines
45
Figure 11. Intel 855PM MCH Source Synchronous Signals Recommended Escape Routing Example
47
Figure 12. Processor Source Synchronous Signals Recommended Escape Routing Example
48
Figure 13. Processor to Intel 855PM MCH Source Synchronous Signals Routing Example
49
Trace Length Equalization Procedures
50
Figure 14. Reference Trace Length Selection
50
Asynchronous Signals
51
Topologies
51
Figure 15. Trace Length Equalization Procedures with Allegro
51
Figure 16. Routing Illustration for Topology 1A
52
Table 8. Layout Recommendations for Topology 1A
52
Topology 1A: Open Drain (OD) Signal Driven by the Processor - IERR
52
Figure 17. Routing Illustration for Topology 1B
53
Table 9. Layout Recommendations for Topology 1B
53
Topology 1B: Open Drain (OD) Signals Driven by the Processor - FERR# and THERMTRIP
53
Figure 18. Routing Illustration for Topology 1C
54
Table 10. Layout Recommendations for Topology 1C
54
Topology 1C: Open Drain (OD) Signals Driven by the Processor - PROCHOT
54
Figure 19. Routing Illustration for Topology 2A
55
Table 11. Layout Recommendations for Topology 2A
55
Topology 2A: Open Drain (OD) Signal Driven by Intel 82801DBM ICH4-M - PWRGOOD
55
Figure 20. Routing Illustration for Topology 2B
56
Table 12. Layout Recommendations for Topology 2B
56
Topology 2B: CMOS Signals Driven by Intel 82801DBM ICH4-M - DPSLP
56
Figure 21. DPSLP# Layout Routing Example
57
Figure 22. Routing Illustration for Topology 2C
58
Table 13. Layout Recommendations for Topology 2C
58
Topology 2C: CMOS Signals Driven by Intel 82801DBM ICH4-M - LINT0/INTR, LINT1/NMI, A20M#, IGNNE#, SLP#, SMI#, and STPCLK
58
Figure 23. Routing Illustration for Topology 3
59
Table 14. Layout Recommendations for Topology 3
59
Topology 3: CMOS Signals Driven by Intel 82801DBM ICH4-M to Processor and FWH - INIT
59
Voltage Translation Logic
60
Processor RESET# Signal
60
Figure 24. Voltage Translation Circuit
60
Figure 25. Processor RESET# Signal Routing Topology with no ITP700FLEX Connector
61
Figure 26. Processor RESET# Signal Routing Topology with ITP700FLEX Connector
61
Figure 27. Processor RESET# Signal Routing Example with ITP700FLEX Debug Port
62
Processor RESET# Routing Example
62
Table 15. Processor RESET# Signal Routing Guidelines with ITP700FLEX Connector
62
Processor and Intel 855PM MCH Host Clock Signals
63
Figure 28. Processor and Intel 855PM MCH Host Clock Layout Routing Example
64
GTLREF Layout and Routing Recommendations
65
Figure 29. Processor GTLREF Voltage Divider Network
65
Figure 30. Processor GTLREF Motherboard Layout
66
Figure 31. Intel 855PM MCH HVREF[4:0] Reference Voltage Generation Circuit
67
Figure 32. Intel 855PM MCH HVREF[4:0] Motherboard Layout
68
AGTL+ I/O Buffer Compensation
69
Processor AGTL+ I/O Buffer Compensation
69
Figure 33. Processor COMP[3:0] Resistor Layout
70
Figure 34. Processor COMP[1:0] Resistor Alternative Primary Side Layout
70
Intel 855PM MCH AGTL+ I/O Buffer Compensation
71
Figure 35. Processor COMP[2] and COMP[0] 18-Mil Wide Dog Bones and Traces
71
Figure 36. Intel 855PM MCH HRCOMP[1:0] Resistor Layout
72
Figure 37. Intel 855PM MCH HSWNG[1:0] Reference Voltage Generation Circuit
72
Processor FSB Strapping
73
Figure 38. Intel 855PM MCH HSWNG[1:0] Layout
73
Figure 39. Processor Strapping Resistor Layout
74
Table 16. ITP Signal Default Strapping When ITP Debug Port Not Used
74
Figure 40. VCCSENSE /V
75
Intel System Validation Debug Support
76
Processor Logic Analyzer Support (FSB LAI)
76
In Target Probe (ITP) Support
76
Background and Justification
76
Implementation
76
Implementation
77
Intel Pentium M Processor and Intel Celeron M Processor On-Die Logic Analyzer Trigger Support (ODLAT)
77
Onboard Debug Port Routing Guidelines
77
Recommended Onboard ITP700FLEX Implementation
78
ITP Signal Routing Guidelines
78
Figure 41. ITP700FLEX Debug Port Signals
79
ITP Signal Routing Example
82
Table 17. Recommended ITP700FLEX Signal Terminations
82
ITP_CLK Routing to ITP700FLEX Connector
83
Figure 42. ITP_CLK to ITP700FLEX Connector Layout Example
84
ITP700FLEX Design Guidelines for Production Systems
85
Figure 43. ITP700FLEX Signals Layout Example
85
Recommended ITP Interposer Debug Port Implementation
86
ITP_CLK Routing to ITP Interposer
86
ITP Interposer Design Guidelines for Production Systems
87
Logic Analyzer Interface (LAI)
87
Figure 44. ITP_CLK to CPU ITP Interposer Layout Example
87
Electrical Considerations
88
Mechanical Considerations
88
Intel Pentium M Processor / Intel Celeron M Processor and Intel 855PM MCH FSB Signal Package Lengths
88
Table 18. Processor and MCH FSB Signal Package Trace Lengths
89
Platform Power Requirements
91
General Description
91
Intel 855PM MCH Phase Lock Loop Power Delivery Design Guidelines
91
Intel 855PM MCH PLL Power Delivery
91
Intel 855PM MCH PLL Voltage Supply Power Sequencing
92
Processor Phase Lock Loop Power Delivery Design Guidelines
92
Processor PLL Power Delivery
92
Figure 45. Intel 855PM MCH 1.8 V V
92
Processor PLL Voltage Supply Power Sequencing
94
Voltage Identification for Intel Pentium M/Intel Celeron M Processor
94
Figure 46. Processor 1.8 V VCCA[3:0] Recommended Power Delivery and Decoupling
94
Figure 47. Intel® Pentium® M Processor / Intel® Celeron® M Processor VID[5:0] Escape Routing Layout Example
95
Table 19. VID Vs. V
96
VCCP Output Requirements
97
VCC-CORE Power Sequencing
97
Figure 48. Power on Sequencing Timing Diagram
97
Figure 49. VCCP Block Diagram
98
Figure 50. VCC-MCH Block Diagram
98
VCC-MCH Output Requirements
98
Thermal Power Dissipation
98
Voltage Regulator Topology
100
Voltage Regulator Design Recommendations
100
Figure 51. Voltage Regulator Multi-Phase Topology Example
100
Figure 52. Buck Voltage Regulator Example
101
Figure 53. High Current Path with Top MOSFET Turned on
101
High Current Path, Top MOSFET Turned on
101
High Current Paths During Abrupt Load Current Changes
101
Figure 54. High Current Path During Abrupt Load Current Changes
102
Figure 55. High Current Path with Top and Bottom Mosfets Turned off (Dead Time)
102
High Current Path with Bottom MOSFET(S) Turned on
102
High Current Paths During Switching Dead Time
102
Figure 56. High Current Path with Bottom MOSFET(S) Turned on
103
General Layout Recommendations
103
Processor Decoupling Recommendations
104
Transient Response
104
High Frequency, MID Frequency, and Bulk Decoupling
105
Figure 57. Estimated Processor Current Consumption Change During STPCLK Exit
105
Processor Core Voltage Plane and Decoupling
106
Figure 58. Intel Pentium M Processor and Intel Celeron M Processorsocket Core Power Delivery Corridor
107
Figure 59. Processor Core Power Delivery and Decoupling Concept
108
Table 20. VCC-CORE Decoupling Guidelines 1
109
Figure 60. VCC-CORE Power Delivery and Decoupling Example - (Primary and Secondary Side Layers)
112
Figure 61. Processor Core Power Delivery "North Corridor" Zoom in View
112
Figure 62. VCC-CORE Power Delivery and Decoupling Example (Layers 3, 5, and 6)
113
Figure 63. Recommended SP Cap Via Connection Layout (Secondary Side Layer)
113
Intel Pentium M Processor / Intel Celeron M Processor and Intel 855PM MCH
114
CCP Voltage Plane and Decoupling
114
Processor
114
Table 21. VCCP Decoupling Guidelines
114
Figure 64. Processor V Power Delivery and Decoupling Concept
116
Ccp
118
Intel 855PM MCH Core Voltage Plane and Decoupling
119
Figure 68. Intel 855PM MCH V
119
Table 22. VCC-MCH Decoupling Guidelines
120
Figure 70. V Power Planes and Decoupling Example
122
Figure 71. V Secondary Layer Decoupling Capacitor Placement (Zoom in View)
123
System Memory Design Guidelines (DDR-SDRAM)
125
Table 23. Intel 855PM Chipset DDR Signal Groups
125
DDR 200/266/333 Mhz System Memory Topology and Layout Design Guidelines
126
Data Signals - SDQ[71:0], SDQS[8:0]
126
Figure 72. Data Signal Routing Topology
127
Table 24. Data Signal Group Routing Guidelines
127
Data to Strobe Length Matching Requirements
129
Table 25. SDQ[71:0] to SDQS[8:0] Length Mismatch Mapping
129
Figure 73. DQ/CB to DQS Trace Length Matching Requirements
130
Strobe to Clock Length Matching Requirements
131
Figure 74. SDQS to SCK/SCK# Trace Length Matching Requirements
132
Data Routing Example
133
Figure 75. Data Signals Group Routing Example
133
Support for Small Form Factor Design DDR Data Bus Routing
134
Control Signals - SCKE[3:0], SCS#[3:0]
134
Table 26. Control Signal to SO-DIMM Mapping
134
Figure 76. Control Signal Routing Topology
135
Table 27. Control Signal Routing Guidelines
135
Control to Clock Length Matching Requirements
136
Figure 77. Control Signal to SCK/SCK# Trace Length Matching Requirements
137
Control Routing Example
138
Figure 78. Control Signals Group Routing Example
138
Command Signals - SMA[12:0], SBS[1:0], SRAS#, SCAS#, SWE
139
Command Topology 1 Solution
139
Figure 79. Command Signal Routing for Topology 1
139
Routing Description for Command Topology 1
139
Table 28. Command Topology 1 Routing Guidelines
140
Command Topology 1 to Clock Length Matching Requirements
141
Figure 80. Command Signal to SCK/SCK# Trace Length Matching Requirements
142
Command Topology 1 Routing Example
143
Figure 81. Command Signals Topology 1 Routing Example
143
Command Topology 2 Solution
144
Figure 82. Command Signal Routing for Topology 2
144
Routing Description for Command Topology 2
144
Table 29. Command Topology 2 Routing Guidelines
145
Command Topology 2 to Clock Length Matching Requirements
146
Figure 83. Command Signal to SCK/SCK# Trace Length Matching Requirements
147
Command Topology 2 Routing Example
148
Figure 84. Command Signals Topology 2 Routing Example
148
Clock Signals - SCK[5:0], SCK#[5:0]
149
Figure 85. DDR Clock Routing Topology (SCK/SCK#[5:0])
149
Table 30. Clock Signal Mapping
149
Table 31. Clock Signal Group Routing Guidelines
150
Clock Signal Length Matching Requirements
151
Figure 86. SCK/SCK# Trace Length Matching Requirements
152
Figure 87. Clock Pair Trace Length Matching Requirements
153
Clock Routing Example
154
Figure 88. Clock Signal Routing Example
154
Intel 855PM Chipset High Density Memory Support
155
Feedback - RCVENOUT#, RCVENIN
155
Figure 89. DDR Feedback (RCVEN#) Routing Topology
155
RCVEN# Routing Example
156
Table 32. Feedback Signal Routing Guidelines
156
Figure 90. RCVEN# Signal Routing Example
157
Support for "DDP Stacked" SO-DIMM Modules
157
Recommended Design Option to Support PC2700 DDR SDRAM with Existing PC1600 and PC2100 Intel 855PM Platforms
158
Shortened Data Signal Group Trace Length
158
Figure 91. Data Signal Group (SDQ[71:0], SDQS[8:0]) Routing Topology - PC2700, PC2100 and PC1600 Compliant
158
Supporting PC2700 Based on an Existing PC Platform Layout
158
Table 33. Data Signal Group (SDQ[71:0], SDQS[8:0]) Routing Guidelines - PC2700, PC2100 and PC1600 Compliant
158
Additional Design Considerations for Adapting Intel 855PM DDR 200/266 Mhz Platforms to Support PC2700
159
Table 34. Existing PC2100/PC1600 DDR SDRAM Design Guidelines Required for PC2700 Support
159
Table 35. Intel 855PM Chipset DDR Signal Package Lengths
160
DDR System Memory Interface Strapping
161
ECC Disable Guidelines
161
Intel 855PM MCH ECC Functionality Disable
161
DDR Memory ECC Functionality Disable
162
DDR Power Delivery
162
SMVREF Generation
162
System Memory Compensation
162
External Thermal Sensor Based Throttling (ETS#)
163
ETS# Usage Model
163
ETS# Design Guidelines
164
Thermal Sensor Placement Guidelines
164
Figure 92. DDR Memory Thermal Sensor Placement
165
Intel 855PM MCH DDR Signal Package Lengths
160
AGP Port Design Guidelines
167
AGP Interface
167
AGP 2.0 Spec
168
AGP Interface Signal Groups
168
Table 36. AGP 2.0 Signal Groups
168
AGP Routing Guidelines
169
Timing Domain Routing Guidelines
169
Table 37. AGP 2.0 Data/Strobe Associations
169
Trace Length Requirements for AGP 1X
169
Trace Length Mismatch
170
Trace Spacing Requirements
170
2X/4X Timing Domain Routing Guidelines
170
Table 38. Layout Routing Guidelines for AGP 1X Signals
170
Trace Length Requirements for AGP 2X/4X
170
Figure 93. AGP Layout Guidelines
171
Trace Spacing Requirements
171
Table 39. Layout Routing Guidelines for AGP 2X/4X Signals
172
Table 40. AGP 2.0 Data Lengths Relative to Strobe Length
172
Trace Length Mismatch Requirements
172
AGP Clock Skew
173
AGP Signal Noise Decoupling Guidelines
173
Table 41. AGP 2.0 Routing Guideline Summary
173
AGP Routing Ground Reference
174
Pull-Ups
174
Table 42. AGP Pull-Up/Pull-Down Requirements and Straps
175
Table 43. AGP 2.0 Pull-Up Resistor Values
175
AGP VDDQ and VREF
176
VREF Generation for AGP 2.0 (2X and 4X)
176
V AGP Interface (2X/4X)
176
AGP Compensation
176
Hub Interface
177
Hub Interface Compensation
177
Hub Interface Data HI[7:0] and Strobe Signals
177
Figure 94. Hub Interface Routing Example
177
Table 44. Hub Interface RCOMP Resistor Values
177
External Layer Routing
178
Internal Layer Routing
178
Table 45. Hub Interface Signals Internal Layer Routing Summary
178
Hub Interface Data HI[10:8] Signals
179
Internal Layer Routing
179
External Layer Routing
179
Terminating HI[11]
179
HIREF/HI_VSWING Generation/Distribution
179
Table 46. Hub Interface Signals External Layer Routing Summary
179
Figure 95. Hub Interface with Single Reference Voltage Divider Circuit
180
Figure 96. Hub Interface with Locally Generated Reference Voltage Divider Circuit
180
Table 47. Hub Interface HIREF/HI_VSWING Generation Circuit Specifications
180
Hub Interface Decoupling Guidelines
181
I/O Subsystem
183
IDE Interface
183
Cabling
183
Primary IDE Connector Requirements
184
Figure 97. Connection Requirements for Primary IDE Connector
184
Secondary IDE Connector Requirements
185
Figure 98. Connection Requirements for Secondary IDE Connector
185
Mobile IDE Swap Bay Support
186
Intel 82801DBM ICH4-M IDE Interface Tri-State Feature
186
S5/G3 to S0 Boot up Procedures for IDE Swap Bay
187
Power down Procedures for Mobile Swap Bay
187
Power up Procedures after Device "Hot" Swap Completed
187
Pci
188
Figure 99. PCI Bus Layout Example
188
Ac'97
188
Figure 100. Intel 82801DBM ICH4-M AC'97 - Codec Connection
189
Figure 101. Intel 82801DBM ICH4-M AC'97 - AC_BIT_CLK Topology
190
Figure 102. Intel 82801DBM ICH4-M AC'97 - AC_SDOUT/AC_SYNC Topology
190
Table 48. AC'97 AC_BIT_CLK Routing Summary
190
Table 49. AC'97 AC_SDOUT/AC_SYNC Routing Summary
191
Table 50. AC'97 AC_SDIN Routing Summary
191
AC'97 Routing
192
Motherboard Implementation
193
Valid Codec Configurations
193
SPKR Pin Configuration
193
Table 51. Supported Codec Configurations
193
Figure 103. Intel 82801DBM ICH4-M AC'97 - AC_SDIN Topology
191
USB 2.0 Guidelines and Recommendations
194
Layout Guidelines
194
General Routing and Placement
194
Figure 104. Example Speaker Circuit
194
USB 2.0 Trace Separation
195
USBRBIAS Connection
195
Figure 105. Recommended USB Trace Spacing
195
USB 2.0 Termination
196
USB 2.0 Trace Length Pair Matching
196
USB 2.0 Trace Length Guidelines
196
Plane Splits, Voids, and Cut-Outs (Anti-Etch)
196
Figure 106. USBRBIAS Connection
196
Table 52. USBRBIAS/USBRBIAS# Routing Summary
196
Table 53. USB 2.0 Trace Length Guidelines (with Common-Mode Choke)
196
GND Plane Splits, Voids, and Cut-Outs (Anti-Etch)
197
VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch)
197
USB Power Line Layout Topology
197
EMI Considerations
198
Common Mode Chokes
198
Figure 107. Good Downstream Power Connection
198
Figure 108. Common Mode Choke Schematic
198
Esd
199
I/O APIC (I/O Advanced Programmable Interrupt Controller)
199
Smbus 2.0/Smlink Interface
200
Smbus Architecture and Design Considerations
201
Smbus Design Considerations
201
Figure 109. SMBUS 2.0/Smlink Protocol
201
General Design Issues/Notes
202
High Power/Low Power Mixed Architecture
202
Calculating the Physical Segment Pull-Up Resistor
202
Figure 110. High Power/Low Power Mixed V
202
Table 54. Bus Capacitance Reference Chart
203
Table 55. Bus Capacitance/Pull-Up Resistor Relationship
203
Fwh
204
FWH Decoupling
204
FWH INIT# Voltage Compatibility
204
In Circuit FWH Programming
204
Figure 111. FWH VPP Isolation Circuitry
205
FWH INIT# Assertion/Deassertion Timings
205
FWH VPP Design Guidelines
205
Figure 112. RTCX1 and SUSCLK Relationship in Intel 82801DBM ICH4-M
206
Figure 113. External Circuitry for Intel 82801DBM ICH4-M Where the Internal RTC Is Not Used
206
Figure 114. External Circuitry for the Intel 82801DBM ICH4-M RTC
207
RTC Crystal
207
Table 56. RTC Routing Summary
207
External Capacitors
208
RTC External Battery Connections
209
RTC Layout Considerations
209
Figure 115. Diode Circuit to Connect RTC External Battery
210
Figure 116. RTCRST# External Circuit for the ICH4-M RTC
210
RTC External RTCRST# Circuit
210
RTC-Well Input Strap Requirements
211
Susclk
211
VBIAS DC Voltage and Noise Measurements
211
Rtc
206
Internal LAN Layout Guidelines
212
Footprint Compatibility
212
Table 57. LAN Component Connections/Features
212
Intel 82801DBM ICH4-M - LAN Connect Interface Guidelines
213
Bus Topologies
213
Figure 117. Intel 82801DBM ICH4-M/Platform LAN Connect Section
213
Table 58. LAN Design Guide Section Reference
213
LOM (LAN on Motherboard) Point-To-Point Interconnect
214
Signal Routing and Layout
214
Figure 118. Single Solution Interconnect
214
Table 59. LAN LOM Routing Summary
214
Crosstalk Consideration
215
Impedances
215
Line Termination
215
Terminating Unused LAN Connect Interface Signals
215
Intel 82562ET / Intel 82562 EM Guidelines
215
Figure 119. LAN_CLK Routing Example
215
Crystals and Oscillators
216
Guidelines for Intel 82562ET / Intel 82562EM Component Placement
216
Intel 82562ET / Intel 82562EM Termination Resistors
216
Critical Dimensions
217
Figure 120. Intel 82562ET / Intel 82562EM Termination
217
Figure 121. Critical Dimensions for Component Placement
217
Distance from Intel 82562ET / 82562ET to Magnetics Module (Distance B)
218
Distance from Magnetics Module to RJ-45 (Distance
218
Reducing Circuit Inductance
218
Figure 122. Termination Plane
219
Terminating Unused Connections
219
Termination Plane Capacitance
219
Intel 82562ET/EM Disable Guidelines
220
Figure 123. Example Intel 82562ET/EM Disable and Power down Circuitry
220
Table 60. Intel 82562ET/EM Control Signals
220
Design and Layout Consideration for Intel 82540EP / 82551QM
221
General Intel 82562ET / 82562EM / 82551QM / 82540EP Differential Pair Trace Routing Considerations
221
Trace Geometry and Length
222
Signal Isolation
222
Figure 124. Trace Routing
222
Magnetics Module General Power and Ground Plane Considerations
223
Figure 125. Ground Plane Separation
223
Common Physical Layout Issues
224
Power Management Interface
225
SYS_RESET# Usage Model
225
PWRBTN# Usage Model
225
Power Well Isolation Control Strap Requirements
225
CPU I/O Signals Considerations
226
Figure 126. RTC Power Well Isolation Control
226
Figure 127. Intel 82801DBM ICH4-M CPU CMOS Signals with CPU and FWH
227
Table 61. Intel 855PM Chipset Clock Groups
229
Platform Clock Routing Guidelines
229
Clock Routing Guidelines
229
Table 62. Platform System Clock Cross-Reference
230
Figure 128. Platform Clock Topology Diagram
231
Clock Group Topology and Layout Routing Guidelines
232
HOST_CLK Clock Group
232
Figure 129. Source Shunt Termination Topology
232
Table 63. BCLK/BCLK#[1:0] Routing Guidelines
233
BCLK Length Matching Requirements
234
BCLK General Routing Guidelines
235
EMI Constraints
235
Figure 130. Clock Skew as Measured from Agent-To-Agent
235
CLK66 Clock Group
236
Figure 131. CLK66 Group Topology
236
Table 64. CLK66 Group Routing Guidelines
236
AGPCLK Clock Group
237
Figure 132. AGPCLK to AGP Connector Topology
237
Figure 133. AGPCLK to AGP Device down Topology
237
CLK33 Clock Group
238
Table 65. AGPCLK Routing Guidelines
238
PCICLK Clock Group
239
Figure 134. CLK33 Group Topology
239
Table 66. CLK33 Group Routing Guidelines
239
Figure 135. PCICLK Group to PCI Device down Topology
240
Table 67. PCICLK Group Routing Guidelines
240
Figure 136. PCICLK Group to PCI Slot Topology
241
Table 68. PCICLK Group Routing Guidelines
241
USBCLK Clock Group
242
Figure 137. USBCLK Group Topology
242
Table 69. USBCLK Routing Guidelines
242
CLK14 Clock Group
243
Clock Chip Decoupling
243
Figure 138. CLK14 Group Topology
243
Table 70. CLK14 Group Routing Guidelines
243
Updates for Systems Based on Intel Pentium M Processor / Intel Celeron M Processor and Intel 855PM Chipset
244
PWRDWN# Signal Connections
244
Platform Power Delivery Guidelines
245
Definitions
245
Platform Power Requirements
246
Platform Power Delivery Architectural Block Diagram
247
Figure 139. Platform Power Delivery Map
247
Voltage Supply
248
Power Management States
248
Intel 855PM MCH / 82801DBM ICH4-M Platform Power-Up Sequence
248
Table 71. Power Management States
248
Figure 140. Intel 855PM/82801DBM Platform Power-Up Sequence
249
Table 72. Timing Sequence Parameters for Figure 140
250
Intel 82801DBM ICH4-M Power Sequencing Requirements
251
1.5 V and 3.3/1.8 V Power Sequencing
251
5REF / 3.3 V Sequencing
251
5Ref_Sus
251
Design Guidelines
251
Figure 141. Example V
251
Figure 142. V5REF_SUS with 5V_ALWAYS Connection Option
252
Figure 143. V5REF_SUS with 3.3V_ALWAYS and VCC5 or VCC5_SUS Connection Option
252
DDR Power Sequencing Requirements
253
Intel 855PM MCH Power Sequencing Requirements
253
Table 73. DDR Power-Up Initialization Sequence
253
DDR Power Delivery Design Guidelines
254
Figure 144. DDR Power Delivery Block Diagram
254
DDR Interface Decoupling Guidelines
255
DDR SO-DIMM System Memory Decoupling Guidelines
255
Intel 855PM MCH VCCSM Decoupling Guidelines
255
V Power Delivery Guidelines
255
DDR Reference Voltage
256
Table 74. Absolute Vs. Relative Voltage Specification
256
Table 75. DDR SDRAM Memory Supply Voltage and Current Specification
257
Table 76. MCH System Memory Supply Voltage and Current Specification
258
SMVREF Design Recommendations
259
Table 77. Termination Voltage and Current Specifications
259
Table 78. Intel 855PM MCH System Memory I/O
260
Table 79. Effects of Varying Resistor Values in the Divider Circuit
260
DDR VREF Requirements
261
Table 80. DDR VREF Calculation
261
Table 81. Reference Distortion Due to Load Current
261
DDR SMRCOMP Resistive Compensation
262
DDR SMRCOMP, SMVREF, VTT 1.25-V Supply Disable in S3/Suspend
262
VTT Rail Power down Sequencing During Suspend
262
VTT Rail Power up Sequencing During Resume
263
DDR VTT Termination
262
Clock Driver Power Delivery Guidelines
263
Figure 145. Decoupling Capacitors Placement and Connectivity
264
Decoupling Recommendations
265
Processor Decoupling Guidelines
265
Intel 855PM MCH Decoupling Guidelines
265
Intel 82801DBM ICH4-M Decoupling Guidelines
265
Table 82. Decoupling Requirements for the Intel 855PM MCH
265
Figure 146. Minimized Loop Inductance Example
266
Table 83. Decoupling Requirements for the Intel 82801DBM ICH4-M
266
DDR VTT High Frequency and Bulk Decoupling
267
AGP Decoupling
267
Hub Interface Decoupling
267
FWH Decoupling
267
General LAN Decoupling
267
CK-408 Clock Driver Decoupling
268
Intel 855PM MCH Power Consumption Numbers
268
Table 84. Intel 855PM MCH Power Consumption Estimates
268
Intel 82801DBM ICH4-M Power Consumption Numbers
269
Table 85. Intel 82801DBM ICH4-M Power Consumption Estimates
269
Thermal Design Power
270
Table 86. Intel 855PM MCH Component Thermal Design Power
270
Table 87. Intel 82801DBM ICH4-M Component Thermal Design Power
270
Intel Pro/Wireless 2100 and Bluetooth Design Requirements
271
PCB Interface Requirements
271
DC Power Requirements for Bluetooth
271
Figure 147. Recommended Topology for Coexistence Traces
271
Selective Suspend Support
272
Wake on Bluetooth Requirements
272
RF Disable Support Requirements for Intel Pro/Wireless 2100 and Bluetooth Devices
272
Reserved, NC, and Test Signals
273
Intel Pentium M Processor and Intel Celeron M RSVD Signals
273
Table 88. Processor RSVD and TEST Signal Pin-Map Locations
273
Intel 855PM MCH RSVD Signals
274
Table 89. MCH RSVD and NC Signal Pin-Map Locations
274
Platform Design Checklist
275
General Information
275
Customer Implementation
276
Design Checklist Implementation
276
Intel Pentium M Processor and Intel Celeron M Processor
277
Resistor Recommendations
277
Figure 148. Processor GTLREF Voltage Divider Network
282
Figure 149. Routing Illustration for INIT
282
Figure 65. Processor
283
Figure 150. Voltage Translation Circuit
283
Figure 151. Routing Illustration for PROCHOT
283
In Target Probe (ITP)
284
ITP700FLEX Connector
284
ITP Interposer
287
Required Strapping When ITP Debug Port Disable
288
Thermal Sensor
288
Decoupling Recommendations
288
Clock Checklist
290
Resistor Recommendations
290
Decoupling Recommendation
292
Figure 152. Clock Power down Implementation
292
Intel 855PM MCH Checklist
293
System Memory
293
MCH System Memory Interface
293
Figure 153. Reference Voltage Level for SMVREF[1:0]
295
DDR SO-DIMM Interface
296
Miscellaneous Signals
298
Figure 154. Intel 855PM MCH HSWNG[1:0] Reference Voltage Generation Circuit
299
Figure 155. Intel 855PM MCH HVREF[4:0] Generation Circuit
299
Resistive Compensation
300
Decoupling Recommendations (MCH)
301
Memory Decoupling Recommendation
301
MCH Reference Voltage
302
AGP Interface
303
Resistor Recommendations
303
AGP Connector
304
AGP Decoupling Recommendations
304
AGP VREF Reference Voltage Dividers
304
Figure 156. AGPREF Implementation (on Intel CRB)
305
ICH4-M Checklist
306
ICH4-M Resistor Recommendations
306
Gpio
308
AGP Busy/Stop Design Requirements
309
System Management Bus (Smbus) Interface
310
AC '97 Interface
311
ICH4-M Power Management Interface
312
FWH/LPC Interface
314
USB Interface
314
Hub Interface
315
Hub Interface Resistor Recommendations
315
Reference Voltage Dividers
315
Figure 157. Hub Interface with Signal Reference Voltage Divider Circuit
316
Figure 158. Hub Interface with Locally Generated Reference Voltage Divider Circuit
316
Figure 66. Intel 855PM MCH
316
14.8.10. RTC Circuitry
317
Figure 159 External Circuitry for the RTC
318
14.8.11. LAN Interface
319
14.8.12. Primary IDE Interface
320
IDE Interface (Secondary IDE Connector)
321
14.8.14. Miscellaneous Signals
322
14.8.15. ICH4-M Power Signals & Decoupling Recommendations
323
USB Checklist
324
Resistor Recommendations
324
Figure 160. USBPWR_CONN[E:A] Design Recommendation
324
Decoupling Recommendations
325
FWH Checklist
325
14.10.1. Resistor Recommendations
325
LAN / Homepna Checklist
326
LAN Interface (82562ET / 82562EM)
326
Resistor Recommendations
326
14.11.1.2. Decoupling Recommendations
327
Figure 161. LAN_RST# Design Recommendation (on Intel CRB)
327
Intel Customer Reference Board Schematics
329
Figure 67. Intel 855PM MCH
330
Advertisement
Advertisement
Related Products
INTEL 852GM -
intel 855GME
Intel 852GME
Intel 852PM
Intel 855GM
Intel 865G
Intel 82496 CACHE CONTROLLER
Intel 80286
Intel 80287
Intel QuickAssist 8920DCC
Intel Categories
Motherboard
Computer Hardware
Server
Server Board
Desktop
More Intel Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL