Ccache - Intel 82496 CACHE CONTROLLER User Manual

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HARDWARE INTERFACE
5.2.2.28. CCACHE#
CCACHE# latched Pentium processor CACHE# signal
A latched version of the Pentium processor CACHE# output signal.
Output from 82496 Cache Controller (pin H01)
Synchronous to ClK
Signal Description
CCACHE# reflects the Pentium processor CACHE# output signal during a CPU cycle on the
memory bus. CCACHE# is active (LOW) during CPU write-backs and CPU cacheable reads.
CCACHE# is undefined for 82496 Cache Controller write back, snoop write back, and
allocation cycles.
CCACHE# is used by the MBC to determine the number of BRDY#s to provide to the CPU.
See Table 5-2.
Table 5-2. CCACHE# Use in Determining the Number of BRDV#s
Number of BRDY#S CCACHE# Read-Only CD/Ct
1 1
x x
1
x
Yes 1
4
0 Yes 0
4
0 No
x
When Driven
CCACHE# is valid from the CLK of CADS# until the CLK of CRDY# or CNA#.
Relation to Other Signals
Pin Symbol Relation to Other Signals
CADS# Address and cycle specification signals (Le., APIC#, CCACHE#, CD/C#, CMIIO#,
CPCD, CPWT, CSCYC, CW/R#, CWAY, KlOCK#, MAP, MBT[3:0j, MCACHE#,
MCFA, MSET, MTAG, NENE#, PAllC#, RDYSRC, and SMlN#) are valid with
CADS#.
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