Map - Intel 82496 CACHE CONTROLLER User Manual

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ntel
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HARDWARE INTERFACE
5.2.2.77. MAP
MAP Memory Bus Address Parity
Indicates Even Memory Bus address parity.
Input when MAOE#=1, Output when MAOE#=O to/from 82496 Cache Controller
(pin U08)
Input synchronous to CLK, SNPCLK or SNPSTB#;
Output synchronous to CLK, MAOE#
active
and MALE high.
Signal Description
MAP indicates the address parity of the 82496 Cache Controller line address bits (i.e., MSET,
MTAG, MCFA). During snoop cycles, MAP is driven by the MBC and indicates the line
address parity for the snooped address.
When Sampled/Driven
MAP is driven by the 82496 Cache Controller on all 82496 Cache Controller initiated cycles
(i.e., when MAOE# is active).
In synchronous snoop mode, MAP is sampled on the rising edge of the first CLK in which
SNPSTB# becomes active. In clocked mode, MAP is sampled on the rising edge of the first
SNPCLK in which SNPSTB# becomes active. In strobed mode, MAP is sampled on the falling
edge of SNPSTB#.
MAP is only sampled with SNPSTB# activation. When SNPSTB# is not asserted, MAP is a
"don't care" signal and is not required to meet set-up and hold times.
Relation to Other Signals
Pin Symbol,
Relation to Other Signals
CADS# Address and cycle specification signals (Le" APIC#, CCACHE#, CD/C#, CM/IO#,
CPCD, CPWT, CSCYC, CW/R#, CWAY, KLOCK#, MAP, MBT[3:0j, MCACHE#,
MCFA, MSET, MTAG, NENE#, PALLC#, RDYSRC, and SMLN#) are
valid
with
CADS#.
MALE MALE and MAOE# together
provide
full control
over
the 82496 Cache Controller
line address output latch and the memory bus address parity (MAP) latch. MALE
controls the latch enable of the memory bus line address parity input.
MAOE#
MALE and MAOE# together provide full control over the 82496 Cache Controller
line address output latch and the memory bus address parity (MAP) latch. MAOE#
provides the output enable for the memory line address parity latch.
MAP is an input when MAOE# is high, and an output when MAOE# is low.
MAPERR# MAPERR# is driven
active
only after a wrong line address parity is driven to the
82496 Cache Controller on the MAP input during a snoop cycle.
SNPSTB# MAP is sampled with SNPSTB# activation.
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