Adsc - Intel 82496 CACHE CONTROLLER User Manual

i
ntel
<f!>
HARDWARE INTERFACE
5.2.2.4.
ADSC#
ADSC# Address Strobe
Indicates the start of a CPU cycle to the cache controller.
Output from Pentium processor (pin N04)
Synchronous to ClK
Signal Description
This signal is functionally identical to the Pentium processor ADS# output signal, and is
connected to the 82496 Cache Controller ADS# input. Refer to the Pentium™ Processor Data
Book for a detailed description of the ADS# signal.
I
5-41