Sign In
Upload
Manuals
Brands
INTEL Manuals
Computer Hardware
852GM -
INTEL 852GM - Manuals
Manuals and User Guides for INTEL 852GM -. We have
2
INTEL 852GM - manuals available for free PDF download: Design Manual, User Manual
INTEL 852GM - Design Manual (365 pages)
Chipset Platform
Brand:
INTEL
| Category:
Computer Hardware
| Size: 5.14 MB
Table of Contents
Table of Contents
3
Revision History
17
1 Introduction
19
Terminology
19
Referenced Documents
20
2 System Overview
21
Intel ® 852GM Chipset Platform System Features
21
Processor Interface
22
Mobile Intel Celeron Processor
22
Figure 1. Intel 852GM Chipset System Block Diagram
22
Mobile Intel Pentium 4 Processor-M
23
Intel Celeron M Processor
23
Intel 852GM Graphics Memory Controller Hub
24
Processor Front Side Bus Support
24
Integrated System Memory DRAM Controller
24
Integrated Graphics Controller
24
Packaging/Power
25
I/O Controller Hub (ICH4-M)
25
Packaging/Power
26
3 General Design Considerations
27
Nominal Board Stack-Up
27
Figure 2. Recommended Board Stack-Up Dimensions
28
Alternate Stack Ups
29
4 Mobile Intel Pentium 4 Processor-M and Mobile Intel Celeron Processor FSB Design Guidelines
31
Processor Front Side Bus (FSB) Routing Guidelines
31
Table 1. Front Side Bus Routing Summary for the Processor
31
Figure 3. Cross-Sectional View of 2:1 Ratio
32
Return Path Evaluation
33
Processor Configuration
33
General Topology and Layout Design Guidelines
33
Source Synchronous (SS) Signal Group
34
Figure 4. Processor Topology
34
Source Synchronous Data Group
34
Source Synchronous Address Group
35
Table 2. Processor Front Side Bus Data Signal Routing Guidelines
35
Table 3. Processor Front Side Bus Address Signal Routing Guidelines
35
FSB Data and Address Routing Example
36
Figure 5. SS Topology for Address and Data
36
Figure 6. FSB Host Data Routing Example Layer 3
36
Figure 7. FSB Host Address Routing Example Layer 3
37
Figure 8. FSB Host Data Routing Example Layer 6
37
Figure 9. FSB Host Address Routing Example Layer 6
38
Common Clock (CC) AGTL+ Signal Group
39
Asynchronous AGTL+ Signals
39
Table 4. Processor Front Side Bus Control Signal Routing Guidelines
39
Topology 1A: Open Drain (OD) Signals Driven by the Processor - IERR# and FERR
39
Figure 10. Routing Illustration for Topology 1A
40
Table 5. Layout Recommendations for Topology 1A
40
Topology 1B: Open Drain (OD) Signals Driven by the Processor - THERMTRIP
40
Figure 11. Routing Illustration for Topology 1B
41
Table 6. Layout Recommendations for Topology 1B
41
Topology 1C: Open Drain (OD) Signals Driven by the Processor - PROCHOT
41
Figure 12. Routing Illustration for Topology 1C
42
Table 7. Layout Recommendations for Topology 1C
42
Topology 2A: Open Drain (OD) Signals Driven by ICH4-M - PWRGOOD
42
Figure 13. Routing Illustration for Topology 2A
43
Figure 14. Routing Illustration for Topology 2B
43
Table 8. Layout Recommendations for Topology 2A
43
Table 9. Layout Recommendations for Topology 2B
43
Topology 2B: CMOS Signals Driven by ICH4-M - DPSLP
43
Figure 15. Routing Illustration for Topology 2C
44
Table 10. Layout Recommendations for Topology 2C
44
Topology 2C: CMOS Signals Driven by ICH4-M - A20M#, IGNNE#, LINT0/INTR, LINT1/NMI, SLP#, SMI#, and STPCLK
44
Topology 3: CMOS Signals Driven by ICH4-M to CPU and FWH - INIT
44
ITP Debug Port
45
Figure 16. Routing Illustration for Topology 3
45
Figure 17. Voltage Translation Circuit for 3.3-V Receivers
45
Table 11. Layout Recommendations for Topology 3
45
Logic Analyzer Interface (LAI)
46
Electrical Considerations
46
Mechanical Considerations
46
Mobile Intel Pentium 4 Processor-M and Intel 852GM Chipset FSB Signal Package Lengths
46
Table 12. Mobile Intel Pentium 4 Processor-M and Intel 852GM Chipset Package Lengths
46
AGTL+ I/O Buffer Compensation
50
Figure 18. GTLREF Routing
50
Figure 19. Mobile Intel Pentium 4 Processor-M COMP[1:0] Resistive Compensation
51
Mobile Intel Pentium 4 Processor-M AGTL+ I/O Buffer Compensation
51
Mobile Intel Pentium 4 Processor-M GTLREF Layout and Routing Recommendations
50
5 Intel Celeron M Processor Front Side Bus Design Guidelines
52
Intel Celeron M Processor Front Side Bus Design Recommendations
52
Recommended Stack-Up Routing and Spacing Assumptions
52
Trace Space to Trace - Reference Plane Separation Ratio
52
Trace Space to Trace Width Ratio
53
Common Clock Signals
53
Processor Common Clock Signal Package Length Compensation
54
Table 13. FSB Common Clock Signal Internal Layer Routing Guidelines
54
Figure 20. Common Clock Topology
55
Table 14. Processor and GMCH FSB Common Clock Signal Package Lengths and Minimum Board Trace Lengths
55
Source Synchronous Signals General Routing Guidelines
56
Figure 21. Layer 6 FSB Source Synchronous Signals GND Referencing to Layer 5
57
Figure 22. Layer 3 FSB Source Synchronous Signals
58
Package Length Compensation
58
Source Synchronous Signal Length Matching Constraints
58
Source Synchronous - Data Group
59
Table 15. Processor FSB Data Source Synchronous Signal Trace Length Mismatch Mapping
59
Source Synchronous - Address Group
60
Table 16. FSB Source Synchronous Data Signal Routing Guidelines
60
Table 17. Processor FSB Address Source Synchronous Signal Trace Length Mismatch Mapping
60
Intel Celeron M Processor and Intel 852GM Chipset GMCH FSB Signal Package Lengths
61
Table 18. Processor FSB Source Synchronous Address Signal Routing Guidelines
61
Table 19. Intel Celeron M Processor and GMCH Source Synchronous FSB Signal Package Lengths
62
Asynchronous Signals
64
Table 20. Asynchronous AGTL+ Nets
64
Figure 23. Routing Illustration for Topology 1A
65
Table 21. Layout Recommendations for Topology 1A
65
Topology 1A: Open Drain (OD) Signals Driven by the Processor - IERR
65
Topology 1B: Open Drain (OD) Signals Driven by the Processor - FERR# and THERMTRIP
65
Figure 24. Routing Illustration for Topology 1B
66
Table 22. Layout Recommendations for Topology 1B
66
Topology 1C: Open Drain (OD) Signals Driven by the Processor - PROCHOT
66
Figure 25. Routing Illustration for Topology 1C
67
Figure 26. Routing Illustration for Topology 2A
67
Table 23. Layout Recommendations for Topology 1C
67
Topology 2A: Open Drain (OD) Signals Driven by ICH4-M - PWRGOOD
67
Figure 27. Routing Illustration for Topology 2B
68
Table 24. Layout Recommendations for Topology 2A
68
Table 25. Layout Recommendations for Topology 2B
68
Topology 2B: CMOS Signals Driven by ICH4-M - DPSLP
68
Topology 2C: CMOS Signals Driven by ICH4-M - LINT0/INTR, LINT1/NMI, A20M#, IGNNE#, SLP#, SMI#, and STPCLK
68
Figure 28. Routing Illustration for Topology 2C
69
Table 26. Layout Recommendations for Topology 2C
69
Topology 3: CMOS Signals Driven by ICH4-M to CPU and FWH - INIT
69
Figure 29. Routing Illustration for Topology 3
70
Table 27. Layout Recommendations for Topology 3
70
Voltage Translation Logic
70
Processor RESET# Signal
71
Figure 30. Voltage Translation Circuit
71
Figure 31. Processor RESET# Signal Routing Topology with no ITP700FLEX Connector
71
Figure 32. Processor RESET# Signal Routing Topology with ITP700FLEX Connector
72
Processor RESET# Routing Example
72
Table 28. Processor RESET# Signal Routing Guidelines with ITP700FLEX Connector
72
Processor and GMCH Host Clock Signals
73
Figure 33. Processor RESET# Signal Routing Example with ITP700FLEX Debug Port
73
Processor GTLREF Layout and Routing Recommendations
74
Figure 34. Processor and GMCH Host Clock Layout Routing Example
74
Figure 35. Processor GTLREF Voltage Divider Network
75
AGTL+ I/O Buffer Compensation
76
Processor AGTL+ I/O Buffer Compensation
76
Figure 36. Processor GTLREF Motherboard Layout
76
Figure 37. Processor COMP[2] & COMP[0] Resistive Compensation
77
Figure 38. Processor COMP[3] & COMP[1] Resistive Compensation
77
Figure 39. Processor COMP[3:0] Resistor Layout
78
Figure 40. Processor COMP[1:0] Resistor Alternative Primary Side Layout
78
Intel Celeron M Processor Front Side Bus Strapping and Debug Port
79
Figure 41. COMP2 & COMP0 27.4-Ω Traces
79
Processor V CCSENSE /V
80
Design Recommendations
80
Sssense
80
Figure 42. VCCSENSE /V
80
Table 29. ITP Signal Default Strapping When ITP Debug Port Not Used
80
6 Processor Power Delivery Requirements
81
7 System Memory Design Guidelines (DDR-SDRAM)
83
Table 30. Intel 852GM GMCH Chipset DDR Signal Groups
83
Length Matching and Length Formulas
84
Package Length Compensation
84
Table 31. Length Matching Formulas
84
Topologies and Routing Guidelines
85
Clock Signals - SCK[4,3,1,0], SCK#[4,3,1,0]
85
Clock Topology Diagram
85
Figure 43. DDR Clock Routing Topology SCK/SCK#[5:0]
85
Table 32. Clock Signal Mapping
85
DDR Clock Routing Guidelines
86
Table 33. Clock Signal Group Routing Guidelines
86
Clock Length Matching Requirements
87
Clock Reference Lengths
87
Figure 44. DDR Clock Trace Length Matching Diagram
88
Clock Package Length Table
89
Clock Routing Example
89
Table 34. DDR Clock Package Lengths
89
Clock Routing Updates for "DDP Stacked" Memory Device Support
90
Data Signals - SDQ[64:0], SDM[7:0], SDQS[7:0]
90
Figure 45. Clock Signal Routing Example
90
Data Bus Topology
92
Figure 46. Data Signal Routing Topology
92
Table 35. Data Signal Group Routing Guidelines
93
SDQS to Clock Length Matching Requirements
94
Data to Strobe Length Matching Requirements
95
Figure 47. SDQS to Clock Trace Length Matching Diagram
95
SDQ to SDQS Mapping
96
Table 36. SDQ/SDM to SDQS Mapping
96
Figure 48. SDQ/SDM to SDQS Trace Length Matching Diagram
97
SDQ/SDQS Signal Package Lengths
98
Table 37. DDR SDQ/SDM/SDQS Package Lengths
98
Control Signals - SCKE[3:0], SCS#[3:0]
100
DDR Data Routing Example
100
Figure 49. Data Signals Group Routing Example
100
Control Signal Topology
101
Figure 50. Control Signal Routing Topology
101
Table 38. Control Signal to SO-DIMM Mapping
101
Control Signal Routing Guidelines
102
Table 39. Control Signal Routing Guidelines
102
Control to Clock Length Matching Requirements
103
Figure 51. Control Signal to Clock Trace Length Matching Diagram
104
DDR Control Routing Example
105
Figure 52. Control Signals Group Routing Example
105
Command Signals - SMA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE
106
Command Topology 1
106
Control Group Package Length Table
106
Table 40. Control Group Package Lengths
106
Figure 53. Command Routing for Topology 1
107
Command Topology 1 Routing Guidelines
108
Table 41. Command Topology 1 Routing Guidelines
108
Command Topology 1 Length Matching Requirements
109
Figure 54. Topology 1 Command Signal to Clock Trace Length Matching Diagram
110
Command Topology 2
111
Figure 55. Command Routing Topology 2
111
Command Topology 2 Routing Guidelines
112
Table 42. Command Topology 2 Routing Guidelines
112
Command Topology 2 Length Matching Requirements
113
Figure 56. Topology 2 Command Signal to Clock Trace Length Matching Diagram
114
Command Topology 2 Routing Example
115
Figure 57. Example of Command Signal Group
115
Command Topology 3
116
Figure 58. Command Routing Topology 3
116
Command Topology 3 Routing Guidelines
117
Table 43. Command Topology 3 Routing Guidelines
117
Command Topology 3 Length Matching Requirements
118
Figure 59. Topology 3 Command Signal to Clock Trace Length Matching Diagram
119
Command Group Package Length Table
120
Table 44. Command Group Package Lengths
120
CPC Signals - SMA[5,4,2,1], SMAB[5,4,2,1]
121
Table 45. CPC Signal to SO-DIMM Mapping
121
CPC Signal Routing Guidelines
122
CPC Signal Topology
122
Figure 60. Command Per Clock Signal Routing Topology
122
Table 46. CPC Signal Routing Guidelines
122
CPC to Clock Length Matching Requirements
123
Figure 61. CPC Signals to Clock Length Matching Diagram
124
CPC Group Package Length Table
125
Feedback - RCVENOUT#, RCVENIN
125
System Memory Compensation
125
SMVREF Generation
125
DDR Power Delivery
125
Table 47. CPC Group Package Lengths
125
External Thermal Sensor Based Throttling (ETS#)
126
ETS# Design Guidelines
126
ETS# Usage Model
126
Figure 62. DDR Memory Thermal Sensor Placement
127
Thermal Sensor Placement Guidelines
127
8 Integrated Graphics Display Port
129
Analog RGB/CRT Guidelines
129
Ramdac/Display Interface
129
Reference Resistor (REFSET)
129
RAMDAC Board Design Guidelines
130
RAMDAC Routing Guidelines
131
Figure 63. GMCH RAMDAC Routing Guidelines with Docking Connector
131
Figure 64. RAMDAC Routing W/ Resistor and Analog Switch Layout Example for Docking Connector
132
DAC Power Requirements
133
Figure 65. Rset Resistor Placement
133
Table 48. Recommended GMCH RAMDAC Components
133
HSYNC and VSYNC Design Considerations
134
DDC and I2C Design Considerations
134
LVDS Transmitter Interface
134
Length Matching Constraints
135
Table 49. Signal Group and Signal Pair Names
135
Table 50. LVDS Signal Trace Length Matching Requirements
135
Package Length Compensation
136
LVDS Routing Guidelines
136
Table 51. LVDS Signal Group Routing Guidelines
136
Table 52. LVDS Package Lengths
137
Digital Video out Port
138
DVO Interface Signal Groups
138
DVOC Interface Signals
138
DVO Port Interface Routing Guidelines
139
Length Mismatch Requirements
139
Package Length Compensation
139
Table 53. DVO Interface Trace Length Mismatch Requirements
139
DVO Routing Guidelines
140
Table 54. DVOC Routing Guideline Summary
140
DVO Port Termination
141
DVO GMBUS and DDC Interface Considerations
141
Table 55. DVOC Interface Package Lengths
141
Leaving the DVO Port Unconnected
142
Miscellaneous Input Signals and Voltage Reference
142
Table 56. GMBUS Pair Mapping and Options
142
Figure 66. GVREF Reference Voltage
143
9 Hub Interface
145
Hub Interface Compensation
145
Figure 67. Hub Interface Routing Example
145
Table 57. Hub Interface RCOMP Resistor Values
145
Hub Interface Data HL[10:0] and Strobe Signals
146
HL[10:0] and Strobe Signals Internal Layer Routing
146
Table 58. Hub Interface Signals Internal Layer Routing Summary
146
Table 59. Hub Interface Package Lengths for ICH4-M
147
Table 60. Hub Interface Package Lengths for GMCH
147
Terminating HL[11]
148
Hub VREF/VSWING Generation/Distribution
148
Single Generation Voltage Reference Divider Circuit
148
Table 61. Hub Interface VREF/VSWING Reference Voltage Specifications
148
Locally Generated Voltage Reference Divider Circuit
149
Figure 68. Single VREF/VSWING Voltage Generation Circuit for Hub Interface
149
ICH4-M Single Generated Voltage Reference Divider Circuit
149
Table 62. Recommended Resistor Values for Single VREF/VSWING Divider Circuit
149
GMCH Single Generated Voltage Reference Divider Circuit
150
Separate GMCH and ICH4-M Voltage Divider Circuits for VREF and VSWING
150
Figure 69. ICH4-M Locally Generated Reference Voltage Divider Circuit
150
Figure 70. GMCH Locally Generated Reference Voltage Divider Circuit
150
Separate ICH4-M Voltage Divider Circuits for HIVREF and HI_VSWING
150
Figure 71. Individual HIVREF and HI_VSWING Voltage Reference Divider Circuits for ICH4-M
151
Figure 72. Individual HLVREF and PSWING Voltage Reference Divider Circuits for GMCH
151
Separate GMCH Voltage Divider Circuits for HLVREF and PSWING
151
Table 63. Recommended Resistor Values for HIVREF and HI_VSWING Divider Circuits for ICH4-M
151
Hub Interface Decoupling Guidelines
152
Table 64. Recommended Resistor Values for HLVREF and PSWING Divider Circuits for GMCH
152
10 I/O Subsystem
153
IDE Interface
153
Cabling
153
Primary IDE Connector Requirements
154
Figure 73. Connection Requirements for Primary IDE Connector
154
Secondary IDE Connector Requirements
155
Mobile IDE Swap Bay Support
155
Figure 74. Connection Requirements for Secondary IDE Connector
155
ICH4-M IDE Interface Tri-State Feature
156
Power down Procedures for Mobile Swap Bay
157
Power-Up Procedures after Device "Hot" Swap Completed
157
S5/G3 to S0 Power-Up Procedures for IDE Swap Bay
157
Pci
158
Ac'97
158
Figure 75. PCI Bus Layout Example
158
Figure 76. ICH4-M AC'97 - Codec Connection
159
Figure 77. ICH4-M AC'97 - AC_BIT_CLK Topology
160
Figure 78. ICH4-M AC'97 - AC_SDOUT/AC_SYNC Topology
160
Table 65. AC'97 AC_BIT_CLK Routing Summary
160
Figure 79. ICH4-M AC'97 - AC_SDIN Topology
161
Table 66. AC'97 AC_SDOUT/AC_SYNC Routing Summary
161
Table 67. AC'97 AC_SDIN Routing Summary
161
AC'97 Routing
162
Motherboard Implementation
163
Valid Codec Configurations
163
SPKR Pin Configuration
163
Table 68. Supported Codec Configurations
163
USB 2.0 Guidelines and Recommendations
164
Layout Guidelines
164
Figure 80. Example Speaker Circuit
164
General Routing and Placement
164
Figure 81. Recommended USB Trace Spacing
165
USB 2.0 Trace Separation
165
USBRBIAS Connection
165
USB 2.0 Termination
166
USB 2.0 Trace Length Guidelines
166
USB 2.0 Trace Length Pair Matching
166
Plane Splits, Voids, and Cut-Outs (Anti-Etch)
166
Figure 82. USBRBIAS Connection
166
Table 69. USBRBIAS/USBRBIAS# Routing Summary
166
Table 70. USB 2.0 Trace Length Preliminary Guidelines (with Common Mode Choke)
166
GND Plane Splits, Voids, and Cut-Outs (Anti-Etch)
167
VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch)
167
USB Power Line Layout Topology
167
EMI Considerations
168
Common Mode Chokes
168
Figure 83. Good Downstream Power Connection
168
Figure 84. Common Mode Choke Schematic
168
Esd
169
IOAPIC (I/O Advanced Programmable Interrupt Controller)
169
IOAPIC Disabling Options
170
Recommended Implementation
170
Smbus 2.0/Smlink Interface
170
Figure 85. Minimum IOAPIC Disable Topology
170
Smbus Architecture and Design Considerations
171
Figure 86. SMBUS 2.0/Smlink Protocol
171
Smbus Design Considerations
171
Calculating the Physical Segment Pull-Up Resistor
172
Figure 87. High Power/Low Power Mixed V
172
General Design Issues and Notes
172
High Power and Low Power Mixed Architecture
172
Fwh
173
FWH Decoupling
173
Table 71. Bus Capacitance Reference Chart
173
Table 72. Bus Capacitance/Pull-Up Resistor Relationship
173
In Circuit FWH Programming
174
FWH INIT# Voltage Compatibility
174
Figure 88. Voltage Translation Circuit for 3.3-V Receivers
174
FWH V PP Design Guidelines
175
Rtc
175
Figure 89. FWH VPP Isolation Circuitry
175
Figure 90. RTCX1 and SUSCLK Relationship in ICH4-M
175
Figure 91. External Circuitry for the ICH4-M Where the Internal RTC Is Not Used
176
Figure 92. External Circuitry for the ICH4-M RTC
176
RTC Crystal
176
External Capacitors
177
Table 73. RTC Routing Summary
177
RTC External Battery Connections
178
RTC Layout Considerations
178
Figure 93. Diode Circuit to Connect RTC External Battery
179
Figure 94. RTCRST# External Circuit for the ICH4-M RTC
179
RTC External RTCRST# Circuit
179
RTC-Well Input Strap Requirements
180
Susclk
180
VBIAS DC Voltage and Noise Measurements
180
Internal LAN Layout Guidelines
181
Figure 95. ICH4-M/Platform LAN Connect Section
181
Table 74. LAN Component Connections/Features
181
Table 75. LAN Design Guide Section Reference
181
ICH4-M - LAN Connect Interface Guidelines
182
10.9.1.1.1. LOM (LAN on Motherboard) Point-To-Point Interconnect
182
Bus Topologies
182
Figure 96. Single Solution Interconnect
182
Crosstalk Consideration
183
Figure 97. LAN_CLK Routing Example
183
Impedances
183
Signal Routing and Layout
183
Table 76. LAN LOM Routing Summary
183
Line Termination
184
Terminating Unused LAN Connect Interface Signals
184
Intel 82562ET / Intel 82562 EM Guidelines
184
Crystals and Oscillators
184
Guidelines for Intel 82562ET / Intel 82562EM Component Placement
184
Critical Dimensions
185
Figure 98. Intel 82562ET / Intel 82562EM Termination
185
Figure 99. Critical Dimensions for Component Placement
185
Intel 82562ET / Intel 82562EM Termination Resistors
185
Distance from Intel 82562ET to Magnetics Module (Distance B)
186
Distance from Magnetics Module to RJ-45 (Distance A)
186
Reducing Circuit Inductance
186
10.9.2.5.1. Terminating Unused Connections
187
10.9.2.5.2. Termination Plane Capacitance
187
Figure 100. Termination Plane
187
Intel 82562ET/EM Disable Guidelines
187
Figure 101. Intel 82562ET/EM Disable Circuitry
188
Table 77. Intel 82562ET/EM Control Signals
188
10.9.4.1.1. Trace Geometry and Length
189
Figure 102. Trace Routing
189
10.9.4.1.2. Signal Isolation
190
10.9.4.1.3. Magnetics Module General Power and Ground Plane Considerations
190
Figure 103. Ground Plane Separation
191
Common Physical Layout Issues
192
General Intel 82562ET/82562EM Differential Pair Trace Routing Considerations
188
Power Management Interface
193
10.10.1. SYS_RESET# Usage Model
193
10.10.2. PWRBTN# Usage Model
193
10.10.3. Power Well Isolation Control Strap Requirements
193
CPU CMOS Considerations
194
Figure 104. RTC Power Well Isolation Control
194
Figure 105. ICH4-M CPU CMOS Signals with CPU and FWH
195
11 Platform Clock Routing Guidelines
197
System Clock Groups
197
Table 78. Individual Clock Breakdown
197
Clock Group Topologies and Routing Constraints
198
Figure 106. Clock Distribution Diagram
198
Figure 107. Source Shunt Termination Topology
199
Table 79. Host Clock Group Routing Constraints
200
Clock to Clock Length Matching and Compensation
201
EMI Constraints
201
Host Clock Group General Routing Guidelines
201
Table 80. Clock Package Length
201
Host Clock Group
199
CLK66 Clock Group
202
Figure 108. CLK66 Clock Group Topology
202
Table 81. CLK66 Clock Group Routing Constraints
202
CLK33 Clock Group
203
Figure 109. CLK33 Group Topology
203
Table 82. CLK33 Clock Group Routing Constraints
203
Figure 110. PCI Clock Group Topology
204
PCI Clock Group
204
Table 83. PCICLK Clock Group Routing Constraints
204
CLK14 Clock Group
205
Figure 111. CLK14 Clock Group Topology
205
Table 84. CLK14 Clock Group Routing Constraints
205
DOTCLK Clock Group
206
Figure 112. DOTCLK Clock Topology
206
Table 85. DOTCLK Clock Routing Constraints
206
Figure 113. SSCCLK Clock Topology
207
SSCCLK Clock Group
207
Table 86. SSCCLK Clock Routing Constraints
207
Figure 114. USBCLK Clock Topology
208
Table 87. USBCLK Clock Routing Constraints
208
USBCLK Clock Group
208
Clock Updates for Intel Celeron M Processor Platforms
209
PWRDWN# Signal Connections
209
12 Intel 852GM Platform Power Delivery Guidelines
211
Definitions
211
Platform Power Requirements
211
Table 88. Power Delivery Definitions
211
Figure 115. Platform Power Delivery Map
212
Platform Power Delivery Architectural Block Diagram
212
Figure 116. Platform Power Delivery Map for Intel Celeron M Processor
213
Voltage Supply
214
Power Management States
214
Power Supply Rail Descriptions
214
Table 89. Power Management States on Intel Reference Board
214
Table 90. Power Supply Rail Descriptions on Intel Reference Board
214
Intel 852GM Platform Power-Up Sequence
215
Processor Power Sequence Requirement
215
GMCH Power Sequencing Requirements
215
ICH4-M Power Sequencing Requirements
216
Figure 117. GMCH Power-Up Sequence
216
Figure 118. ICH4-M Power-Up Sequence
217
3.3 V/1.5 V Power Sequencing
218
5REF Sequencing
218
Table 91. Timing Sequence Parameters for Figure 118
218
5REFSUS Design Guidelines
219
Figure 119. Example V
219
Figure 120. V5REFSUS with +V5ALWAYS Connection Option
219
Sequencing Circuitry
219
DDR Memory Power Sequencing Requirements
220
Figure 121. V5REFSUS with +V3ALWAYS and +V5S or +V5 Connection Option
220
Table 92. DDR Power-Up Initialization Sequence
220
Intel 852GM Platform Power Delivery Guidelines
221
Figure 122. Example for Minimizing Loop Inductance
221
Intel 852GM Decoupling Guidelines
221
Processor Decoupling / Power Delivery Guidelines
221
GMCH VCCSM Decoupling
222
Table 93. GMCH Decoupling Recommendations
222
DDR Memory Power Delivery Design Guidelines
223
DDR SDRAM VDD Decoupling
223
DDR VTT Decoupling Placement and Layout Guidelines
223
2.5-V Power Delivery Guidelines
224
Figure 123. DDR Power Delivery Block Diagram
224
GMCH and DDR SMVREF Design Recommendations
224
DDR SMRCOMP Resistive Compensation
225
Figure 124. GMCH SMRCOMP Resistive Compensation
225
Figure 125. GMCH System Memory Reference Voltage Generation Circuit
225
DDR SMRCOMP, SMVREF, and VTT 1.25-V Supply Disable in S3/Suspend
226
DDR VTT Termination
226
Gmch Gtlvref
226
Other GMCH Reference Voltage and Analog Power Delivery
226
Figure 126. GMCH HDVREF[2:0] Reference Voltage Generation Circuit
227
Figure 127. GMCH HAVREF Reference Voltage Generation Circuit
227
Figure 128. GMCH HCCVREF Reference Voltage Generation Circuit
227
Figure 129. Primary Side of the Motherboard Layout
228
Figure 130. Secondary Side of the Motherboard Layout
228
Figure 131. GMCH HXRCOMP and HYRCOMP Resistive Compensation
229
Figure 132. GMCH HXSWING and HYSWING Reference Voltage Generation Circuit
229
GMCH AGTL+ I/O Buffer Compensation
229
GMCH AGTL+ Reference Voltage
229
GMCH Analog Power
229
Figure 133. Example Analog Supply Filter
230
Table 94. Analog Supply Filter Requirements
230
FWH Decoupling
231
Hub Interface Decoupling
231
ICH4-M Decoupling
231
ICH4-M Decoupling / Power Delivery Guidelines
231
Table 95. ICH4-M Decoupling Requirements
231
General LAN Decoupling
232
13 Reserved, NC, and Test Signals
233
Table 96. Processor "Intel Reserved" Signal Pin-Map Locations
233
Intel 852GM GMCH RSVD Signals
234
Table 97. Intel 852GM RSVD and NC Signal Pin-Map Locations
234
14 Platform Design Checklist
237
General Information
237
Customer Implementation of Voltage Rails
237
Design Checklist Implementation
238
Mobile Intel Pentium 4 Processor-M and Mobile Intel Celeron Processor
239
Resistor Recommendations
239
Figure 134. Routing Illustration for INIT
241
Figure 135. Voltage Translation Circuit for PROCHOT
241
Figure 136. VCCIOPLL, VCCA and VSSA Power Distribution
241
In Target Probe (ITP)
242
Decoupling Recommendations
242
Power-Up Sequence
243
Table 98. Mobile Intel Pentium 4 Processor-M Power-Up Timing Specifications
243
Intel Celeron M Processor
244
Resistor Recommendations
244
Figure 137. Mobile Intel Pentium 4 Processor-M Power up Sequence
244
Figure 138. Routing Illustration for INIT# (for Intel Celeron M Processor)
246
Figure 139. Voltage Translation Circuit for PROCHOT# (for Intel Celeron M Processor)
246
CK-408 Clock Checklist
247
Resistor Recommendations
247
Figure 140. Clock Power-Down Implementation
248
Intel 852GM GMCH Checklist
249
System Memory
249
GMCH System Memory Interface
249
DDR SO-DIMM Interface
250
Figure 141. Reference Voltage Level for SMVREF
250
SODIMM Decoupling Recommendation
251
Fsb
251
Figure 142. Intel 852GM GMCH HXSWING and HYSWING Reference Voltage Generation Circuit
251
Hub Interface
252
Graphics Interfaces
252
Dvo
252
Lvds
252
Figure 143. DPMS Clock Implementation
253
Dac
254
Miscellaneous
254
GMCH Decoupling Recommendations
255
GMCH Power-Up Sequence
256
Figure 144. Intel 852GM GMCH Power-Up Sequence
256
ICH4-M Checklist
257
PCI Interface and Interrupts
257
Gpio
258
AGP_BUSY# Design Requirement
259
Smbus) System Management Interface
259
AC '97 Interface
260
ICH4-M Power Management Interface
261
FWH/LPC Interface
261
USB Interface
262
Hub Interface
262
Figure 145. Single or Locally Generated GMCH & ICH4-M HIVREF/HI_VSWING Circuit
262
14.8.10. RTC Circuitry
263
Figure 146. Single Generated GMCH & ICH4-M VSWING/VREF Reference Voltage/ Local Voltage Divider Circuit for VSWING/VREF
263
14.8.11. LAN Interface
264
Figure 147. External Circuitry for the RTC
264
14.8.12. Primary IDE Interface
265
14.8.13. Secondary IDE Interface
265
14.8.14. Miscellaneous Signals
265
14.8.15. ICH4-M Decoupling Recommendations
266
USB Power Checklist
267
Downstream Power Connection
267
Figure 148. Good Downstream Power Connection
267
FWH Checklist
268
14.10.1. Resistor Recommendations
268
LAN / Homepna Checklist
269
Resistor Recommendations (for 82562ET / 82562EM)
269
14.11.2. Decoupling Recommendations
269
Figure 149. LAN_RST# Design Recommendation
269
15 Schematics
271
Parallel Port
352
Floppy Connector
352
Serial Port
352
Power on Sequence
364
Advertisement
Intel 852GM - User Manual (26 pages)
Small Form Factor Proof-of-Concept Board
Brand:
Intel
| Category:
Computer Hardware
| Size: 0.43 MB
Table of Contents
Table of Contents
3
Revision History
5
Product Overview
6
Introduction
6
Related Documents
6
Product Contents
7
Proof-Of-Concept Board Features
7
SFF POC Board Block Diagram
9
SFF Placement - Top View
10
Installation Guide for POC Board
11
Before You Begin
11
Setting up the SFF POC Board
11
Additional Hardware
11
Assembled Board, Front View
12
Jumper Settings
12
20-Pin Power Supply Connector
14
Connectors and Jumpers
15
SFF POC Board Connectors and Jumpers
15
List of Jumpers
16
SFF POC Board Solder Side
16
Jumpers
16
LCD Voltage Selection (JP2)
17
COM2 RS-232/422/485 Selection (JP3)
17
COM2 RS-232/422/485 Selection (JP4)
17
RI/+5V/+12V Selection (JP5)
17
Clear CMOS (JP1)
17
List of Connectors
18
Connectors
18
USB Connector (CN1)
18
USB Connector (CN2)
19
Primary IDE Hard Drive Connector (CN3)
19
Digital IO Connector (CN4)
20
Front Panel (CN5)
20
Serial Port COM2 Connector (CN6) RS-232 Mode
20
Serial Port COM2 Connector (CN6) RS-422 Mode
20
Serial Port COM2 Connector (CN6) RS-485 Mode
21
Parallel Port Connector (CN7)
21
Dual Channel LVDS Connector (CN8)
21
Power Connector (CN9)
22
TV-Out Connector (CN10)
22
DVI Connector (CN11)
22
Audio Input/Output Connector (CN12)
23
Ethernet 10/100Baset RJ-45 Phone Jack Connector (CN13)
23
External 5VSB/PWRGD Connector (CN14)
23
Irda Connector (CN15)
23
Fan Connector (CN16)
24
Mini-DIN PS/2 Connector (CN17)
24
Serial Port COM1 Connector (CN18)
24
CRT Display Connector (CN19)
25
External Battery (VBA T2)
25
Compact Flash Disk Slot (CFD)
25
Advertisement
Related Products
Intel 855PM
intel 855GME
Intel 852GME
Intel 852PM
Intel 855GM
Intel 8XC196Kx
Intel 8XC196Lx
INTEL 845 CHIPSET PLATFORM FOR SDR - DESIGN GUIDE UPDATE 2004
Intel 80C188EC
Intel 87C196CA
INTEL Categories
Motherboard
Computer Hardware
Server
Server Board
Desktop
More INTEL Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL