Intel 82496 CACHE CONTROLLER User Manual page 110

CHAPTER 4
CACHE INITIALIZATION AND CONFIGURATION
This section describes the physical and mode configurations available when using the 82496
Cache Controller and 82491 Cache SRAM. Physical configuration determines the organization
of the 512-Kbyte or 256-Kbyte cache. Mode configuration determines how the cache core
operates and communicates with the memory bus.
The 82496 Cache Controller supports a wide variety of physical configurations and a variety
of mode configurations. Physical and mode configuration decisions are based on arriving at a
desired balance between performance and memory bus controller design complexity and cost.
Figure 4-1 summarizes the basic configurations available when using the 82496 Cache
Controller/82491 Cache SRAM with the Pentium processor.
I
MEMORY BUS = 64 BITS MEMORY BUS = 128 BITS
256 KBYTE
CACHE
SIZE
512 KBYTE
CACHE
SIZE
4 TRANS.
LR= 1
TAGS=8K
LIS
=
1
LR=1
TAGS = 8K
LIS
=
2
#1
#3
8 TRANS.
LR=2
TAGS=4K
LIS
=
1
LR=2
TAGS=8K
LIS
=
1
#1 • #5 = CACHE CONFIGURATION NUMBERS
#2
#4
4 TRANS.
LR=2
TAGS =8K
LIS
=
1
4/8
TRANS. = NUMBER OF BURST CYCLES FOR LlNEFILLlWRITE BACK
LR = 82496/PENTIUM ™ PROCESSOR LINE RATIO
LIS = 82496 LINES PER SECTOR
NUMBER OF 82491 DEVICES
III
= NOT SUPPORTED
8 TRANS.
LR =4
TAGS=4K
LIS
=
1
CDB9
Figure 4-1. 82491 Cache Controller/82491 Cache SRAM Configurations with the
Pentium™ Processor
4-1