82491 Cache Sram Parity Devices - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
TO CPU
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BRDY#
MBRDY#
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BURST
COUNT
BURST
COUNT
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LATCH
DATA TO CPU MUX
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DATA FROM MEMORY MUX
Figure 5·20. 82491 Cache SRAM Read Data Path
5.1.6.5.
82491 CACHE SRAM PARITY DEVICES
CPU BUS
BUFFER
MEMORY BUFFER
#0 OR #1
CDB40
A 82491 Cache SRAM may be designated as a parity device. This is done be strapping the
MBE#[PAR#] pin low during RESET. Two 82491 Cache SRAM SRAMs are used to provide
the memory bus controller full data parity support.
In data parity configuration, the 82491 Cache SRAM CPU bus pins CDATA[3:0] are
connected to the Pentium processor Data Parity pins (DP[7:0]) and CDATA[7:4] are connected
to the Pentium processor Byte Enable outputs (BE[7:0]). Refer to Figure 5-21.
5·28
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