Signal Synchronization - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
BE[7:4]#
4
CDATA[7:4]
PARITY 82491 #1
CDATA[3:0]
8
BE[7:0]#
PENTIUM ™
PROCESSOR
8
DP[7:0]
4
BE[3:0]#
CDATA[7:4]
PARITY 82491 #2
CDATA[3:0]
CDB30
Figure 5-21. Pentium™ Processor/82491 Cache SRAM Data Parity Connections
5.1.7. Signal Synchronization
The MBC must also provide proper synchronization as needed. The Pentium processor CPU-
Cache Chip Set runs at 66 MHz, along with most of its address and control-related signals,
including CADS#, CDTS#, KWEND#, SWEND#, and CRDY#. Because the 82496 Cache
Controller/82491 Cache SRAM allows the memory system to operate at lower frequency, the
designer may choose to design an asynchronous memory bus running below 66 MHz. Such a
scheme will require synchronization.
Some system designers will choose a divided synchronous memory bus, wherein the memory
system runs at 33 MHz and synchronization is unnecessary.
The following is an example of a synchronization path used in generating KWEND#.
KWEND# is generated to provide the 82496 Cache Controller with the MKEN# and MRO#
parameters. When the 82496 Cache Controller generates the cycle address, the memory system
decodes the address and generates MKEN# and MRO#, based on cacheability and read-only
address maps. These signals are asserted to the 82496 Cache Controller along with
MKWEND#. MKWEND# tells the MBC that MKEN# and MRO# are valid and that
KWEND# must be generated. Since the MKWEND# is synchronous with the memory bus, it
must be synchronized to become KWEND#. KWEND# then causes the 82496 Cache
Controller to sample MKEN# and MRO#.
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