1/0 Cycles; Special Cycles; Flush And Sync Cycles - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.1.1.1.12. 1/0 Cycles
All I/O cycles are transferred to the memory bus and are of length 1 (only 1
MBRDY#/BRDY# are required). The MBC must supply BRDY# to the CPU once the I/O
cycle is complete.
I/O cycles can be pipelined into and out of other I/O and memory bus cycles.
5.1.1.1.13. Special Cycles
Special cycles are treated exactly like I/O cycles. They are not posted, and the MBC must
provide BRDY# to the CPU.
5.1.1.1.14. FLUSH and SYNC Cycles
To the MBC, cycles initiated by the FLUSH# and SYNC# signals resemble replacement write
back cycles and should be handled as such. There is no need to preve.\1t snooping or arbitration
between these cycles.
82496 Cache Controller FLUSH# invalidates the entire 82496 Cache Controller and Pentium
processor tag arrays. Two clocks are required to lookup a tag entry if the result is a miss. The
82496 Cache Controller also invalidates tags in the CPU cache by executing inquire and back-
invalidation cycles to the Pentium processor. There are two reasons for potentially wanting to
assert the CPU FLUSH# in addition to the 82496 Cache Controller FLUSH#. One, if the MBC
wants to see the Pentium processor flush acknowledge special cycle, and two, to assure that no
Pentium processor cache hits are occurring once FLUSH# has been asserted to the 82496
Cache Controller. This is because the 82496 Cache Controller flush operation does not inhibit
Pentium processor cache hit operations. For optimum performance, issue FLUSH# to only the
82496 Cache Controller.
SYNC# will cause both the 82496 Cache Controller/82491 Cache SRAM and Pentium
processor caches to, write back all modified lines. The 82496 Cache Controller causes the CPU
cache to write back all modified data by initiating inquire cycles to the Pentium processor
when the 82496 Cache Controller/82491 Cache SRAM cache line state is modified.
When the MBC decodes a Pentium processor Flush (due to the. INVD or WBINVD
instructions) or Write Back (due to the WBINVD instruction) special cycle, it must provide
FLUSH# to the 82496 Cache Controller. The 82496 Cache Controller/82491 Cache SRAM
treats Flush and Write Back special cycles like I/O cycles. They are not posted, and the MBC
must provide BRDY#. The WBINVD instruction causes the Pentium processor to issue the
Flush special cycle followed by the Write Back special cycle.
To insure that the processor will not generate an additional bus cycle (code prefetch or page
table read) following the INVD or WBINVD instructions, the MBC must delay BRDY# to the
82496 Cache Controller/82491 Cache SRAM for the Flush and Write Back special cycles until
it recognizes CAHOLD asserted. Having the MBC Wait to complete the CPU special cycles
until the flush operation has been internally recognized by the 82496 Cache Controller insures
that no additional CPU or 82496 Cache Controller cycles are generated. The 82496 Cache
Controller flush operation is complete when FSIOUT# becomes inactive. Note that the
Pentium processor will not pipeline any cycle into a Flush or Write Back special cycle.
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