Read Hit; Cacheable Read Miss - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
'This column represents the number of data transfers which the 82491 Cache SRAM will be expecting. In
clocked memory bus mode, the 82491 Cache SRAM uses MBRDY# to transfer data to/from its buffers. In
strobed memory bus mode, any transition on MISTB/MOSTB will cause the 82491 Cache SRAM to
latch/output data. In either mode, MEOC# may replace the last MBRDY#, MISTB, or MOSTB. An "x"
represents either 0 or 1 transfers. The 82491 Cache SRAM will ignore an extra MBRDY#, MISTB, or
MOSTB, if asserted.
The text that follows describes 82496 Cache Controller cycles that both require and do not
require MBC identification and control.
5.1.1.1.1. Read Hit
Read hit cycles are reads to the [M],[E], or [S] cache states. The 82496 Cache
Controller/82491 Cache SRAM returns information to the CPU without wait-states or in one
wait-state, and transparently to the MBC.
During read hit cycles, the 82496 Cache Controller/82491 Cache SRAM returns either a
complete line or a portion of a line to the CPU. If a line is marked read-only and data, the
82496 Cache Controller automatically de-asserts KEN# to the CPU so that the information is
not cached in the Pentium processor data cache. If a line is code (including read-only) or is
non-read-only data, the 82496 Cache Controller will hold KEN# asserted to the CPU to cache
the information in the Pentium processor code or data cache.
5.1.1.1.2, Cacheable Read Miss
Read miss cycles cause the 82496 Cache Controller to assert CADS# and request the needed
code/data from the memory bus. If the information is cacheable in the 82496 Cache
Controller/82491 Cache SRAM, the 82496 Cache Controller asserts the MCACHE# pin to the
MBC. During the cycle, the MBC returns MKEN# active to render the line cacheable.
Because the needed information is cacheable to the CPU and the 82496 Cache
Controller/82491 Cache SRAM, both require a complete cache line of information. The CPU
receives four transfers while the 82496 Cache Controller/82491 Cache SRAM cache receives
four or eight, depending on the configuration.
The exception to this rule is a data line-fill in which MRO# is asserted before the first transfer
or when CCACHE# and CPCD are inactive. When MRO# is asserted with KWEND#, the
82496 Cache Controller/82491 Cache SRAM caches the entire line (four or eight transfers,
depending on the selected configuration). The Pentium processor will, in tum, cache read only
information if D/C# is low (code), but not if D/C# is high (data). If CCACHE# and CPCD are
both inactive, then the line is cacheable by the 82496 Cache Controller/82491 Cache SRAM
and not by the Pentium processor. In this case, the 82496 Cache Controller/82491 Cache
SRAM receives four or eight transfers and the Pentium processor only requires one.
Once the 82496 Cache Controller has snooped the other caches for a possible modified line,
the MBC asserts SWEND# to put the line in an appropriate MESI state. If the snoop results in
a hit to a modified line and the line in the other cache is not invalidated (i.e., SNPINV not
asserted), MWB/WT# is driven low to place the line in the shared state. If the line originated
from another cache without memory being updated, DRCTM# causes a transition to a
modified state.
If both cache WAYS are occupied, the 82496 Cache Controller must initiate a replacement
cycle (described later in this section).
5-6
I