Intel 82496 CACHE CONTROLLER User Manual page 55

PINOUTS
Table 1-10. Pentium™ Processor CPU-Cache Chip Set Brief Pin Descriptions (Contd.)
Symbol Type Part Name and Function
SYNC# I CC
The Synchronize Pentium processor CPU Cache Chip Set signal
synchronizes the 82496 Cache Controller /82491 Cache SRAM tag array
with main memory. All modified cache lines in the 82496 Cache Controller
/82491 Cache SRAM are written back to main memory. SYNC# differs
from FLUSH# in that it doesn't invalidate the 82496 Cache Controller or
Pentium processor tag array. All E,I, and S state lines remain in the E,I,
and S states. All modified cache lines (M state) cause the 82496 Cache
Controller to inquire the CPU (the Pentium processor will write back 'M'
state data to the 82496 Cache Controller /82491 Cache SRAM ) and
become non-modified (E state) by writing modified data to the memory
bus.
SYNC# shares a pin with the Configuration signal MALORV.
TAG[11:0j I/O
CC
See CFA[6:0j.
TCK I CC The Testability Clock input provides the clocking function for the Pentium
I CS processor, 82496 Cache Controller, and 82491 Cache SRAM boundary
I P scan in accordance with the JTAG/Boundary Scan interface (IEEE Std
1149.1 )., It is used to clock state information and data into and out of the
Pentium processor, 82496 Cache Controller, or 82491 Cache SRAM
during boundary scan.
TDI I CC The Test Data Input is a serial input pin for the test logic. TAP instructions
I
CS
and data are shifted into the Pentium processor, 82496 Cache Controller,
I P or 82491 Cache SRAM components on the TOI input pin on the rising
edge of TCK when the TAP controller is in an appropriate state.
TDO 0
CC
The Test Data Output is a serial output of the test logic. TAP instructions
0
CS
and data are shifted out of the Pentium processor, 82496 Cache
0
P Controller, or 82491 Cache SRAM on the TOO pin on the falling edge of
TCK when the TAP controller is in the appropriate state.
TMS I CC The value of the Test Mode Select input signal sampled at the rising edge
I
CS
of TCK controls the sequence of TAP controller state changes for the
I P Pentium processor, 82496 Cache Controller, and 82491 Cache SRAM
components.
TRST# I CC The Test Reset pin. When asserted, it allows the TAP controller to be
I P asynchronously initialized.
W/R# I
CC
Write/Read is one of the primary bus cycle definition pins. It is driven valid
I CS in the same clock as the AOS# signal is asserted. W/R# distinguishes
0
P between write and read cycles.
WAY
0
CC
The 82496 Cache Controller Way indication is used by the 82491 Cache
I CS SRAM to properly load and store buffers as well as update the MRU bit.
WB/WT#
0
CC The WriteBacklWriteThrough signal allows a Pentium processor data
I P cache line to be defined as write back or write through on a line by line
basis. As a result, it determines whether a cache line is initially in the S or
E state in the CPU data cache. This signal provides the L 1/L2 cache
consistency protocol. NOTE: the 82496 Cache Controller forces the
Pentium processor into a write-once mode in order to maintain Modified
data inclusion and assure cache consistency.
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