Iperr - Intel 82496 CACHE CONTROLLER User Manual

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HARDWARE INTERFACE
5.2.2.65.
IPERR#
IPERR# Internal Parity Error
Indicates that a Tag RAM or address path parity error occurred.
Output from 82496 Cache Controller (pin 001)
Synchronous to ClK
Glitch Free
Signal Description
IPERR# is driven active for 82496 Cache Controller TagRAM parity errors, and for internal
address path parity errors.
Each TagRAM "set" has 41 memory bits: 20 bits for way "0" (I5 bits for the tag, 4 for the line
status, and one Read-Only bit), 20 bits for way "1", and one LRU bit. Two parity bits are
associated with each TagRAM set. One parity bit represents the parity information for way "0"
and the other for way "1". Each parity bit is stored adjacent to the 20 bits of the way it
represents (the LRU bit is not covered).
In every lookup cycle, the whole "set" will be read, including the two parity bits. The parity
check will be done outside the TagRAM by regenerating the parity and comparing it to the
read parity bits. In case of an error, the IPERR# signal will be activated.
The parity bits are written in every TagRAM cycle which causes "set" data modification. Since
many of the cycles do partial updates (e.g. a snoop which modifies only the line status, or a
write to E which causes a state transition to M), the 82496 Cache Controller will perform a
Read-Modify-Write cycle to write the parity.
When Driven
IPERR# is always valid and stays active for a minimum of 1 CPU CLK. If internal parity error
checking is desired, IPERR# should always be monitored by the MBC. Since internal parity
can be affected by data path errors as well as internal lookups, this internal parity is always
valid.
IPERR# is inactive during RESET.
Relation to Other Signals
None.
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