Table Title Page - Intel 82496 CACHE CONTROLLER User Manual

Table
3-10.
4-1.
4-2.
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4-5.
4-6.
4-7.
5-1.
5-2.
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CONTENTS
Title Page
MESI State Changes for SNOOP Cycles: 82496'Cache Controller/82491
Cache SRAM to CPU Caches ................................................................................. 3-22
Pentium™ Processor Chip Set Initialization Recommendations ............................... 4-4
82496 Cache Controller/82491 Cache SRAM Configuration Inputs ......................... 4-4
Pentium™ Processor CFA Address Connections ..................................................... 4-7
Memory Bus Address Control ................................................................................... 4-8
MX!MTR Configurations ............................................................................................ 4-9
Parity Configurations ................................................................................................. 4-9
82491 Cache SRAM Address Connections ............................................................ 4-10
Cycle Identification and Length ................................................................................. 5-5
CCACHE# Use in Determining the Number of BRDY#s ......................................... 5-69
Using CPCD and CPWT to Determine Write Hit to [SJ versus Write Miss .............. 5-80
FSIOUT# Operation Priorities ................................................................................. 5-98
Actions Based on 82496 Cache Controller Configuration Test Inputs
(HIGHZ# and SLFTST#) ....................................................................................... 5-100
KEN# Operation ., .................................................................................................. 5-114
82491 Cache SRAM Line Ratio Configuration with LR[1 :OJ .................................. 5-121
MCACHE# Status versus Cycle Type ................................................................... 5-139
Signals Sampled at RESET ....................................... , .......................................... 5-184
SNPNCA Asserted During Snoop Requests (Inactive SNPINV) ........................... 5-198
Snooping Modes ....................................................................................... '" ......... 5-200
Absolute Maximum Ratings ...................................................................................... 7-2
D.C. Specifications .................................................................................................... 7-3
Three Specification Classes, Their Purpose and the New Parameters .................... 7-5
Description of Maximum Flight Time and Clock Skew .............................................. 7-8
Signal Group: CPU to Cache RAM (CPU-CRAM) (66 MHz 256 Kbyte Version) ...... 7-9
Signal Group: CPU to Cache (CPU-Cache) (66 MHz 256 Kbyte Version) ............. 7-10
Signal Group: CPU to Cache Controller (CPU-CCTL)
(66 MHz 256 Kbyte Version) ................................................................................... 7-11
Signal Group: Cache Controller to Cache RAM (CCTL-CRAM)
(66 MHz 256 Kbyte Version) ................................................................................... 7-12
Signal Group: CPU to Cache RAM (CPU-CRAM)
(60 MHz 256 Kbyte Version) ................................................................................... 7-12
Signal Group: CPU to Cache (CPU-Cache)
(60 MHz 256 Kbyte Version) ................................................................................... 7-13
Signal Group: CPU to Cache Controller (CPU-CCTL)
(60 MHz 256 Kbyte Version) ................................................................................... 7-14
Signal Group: Cache Controller to Cache RAM (CCTL-CRAM)
(60 MHz 256 Kbyte Version) ................................................................................... 7-15
Signal Group: CPU to Cache RAM (CPU-CRAM) (60 MHz 512 Kbyte Version) .... 7-15
Signal Group: CPU to Cache (CPU-Cache) (60 MHz 512 Kbyte Version) ............. 7-16
Signal Group: CPU to Cache Controller (CPU-CCTL)
(60 MHz 512 Kbyte Version) ................................................................................... 7-17
Signal Group: Cache Controller to Cache RAM (CCTL-CRAM)
(60 MHz 512 Kbyte Version) ................................................................................... 7-18
Specifications for Signal Quality ............................................................................. 7-20
66 MHz CPU Cache Chip Set Common Timings .................................................... 7-21
66 MHz Pentium™ Processor Memory Bus Interface Timings ................................ 7-23
66 MHz 82496 Cache Controller Memory Bus Interface Timings ........................... 7-24
66 MHz 82491 Cache SRAM Memory Bus Interface Timings ................................ 7-27
60 MHz CPU Cache Chip Set Common Timings .......... , ......................................... 7-32
60 MHz Pentium™ Processor Memory Bus Interface Timings ................................ 7-34
60 MHz 82496 Cache Controller Memory Bus Interface Timings ........................... 7-35
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