Cache-To-Cache Transfer; Read For Ownership - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
the 82496 Cache Controller/8249l Cache SRAM cache will ignore the data that it receives
from the memory bus and supply the data to the CPU from the 82491 Cache SRAM array (in
accordance with the BRDY#s supplied by the MBC). Locked writes are posted like any other
write. Locked cycles, both reads and writes, never change the 82496 Cache Controller tag
state.
The 82496 Cache Controller/8249l Cache SRAM will post locked reads and writes to the
memory bus even when the read
,or
write is a hit. If the locked read is a hit to modified data,
the 82496 Cache Controller/82491 Cache SRAM cache returns data to the CPU, and memory
data is ignored.
Locked cycles are non-cacheable by the CPU and by the 82496 Cache Controller/8249l Cache
'SRAM. For this reason they are treated just like non-cacheable read misses and write misses.
The CSCYC output is only active during locked sequences in which the access is split over two
addresses (LOCK# and SCYC active).
5.1.1.1.10.
Cache-To-Cache Transfer
A cache-to-cache transfer may be done when the 82496 Cache Controller/8249l Cache SRAM
must perform a line fill or allocation by transferring data directly from another cache. The
82496 Cache Controller/8249l Cache SRAM assumes that this data is being updated in main
memory as well. Otherwise, the data must be marked as modified and the cache supplying the
data must invalidate its copy.
If the data is shared with main memory, the caches mark their copies of the data as shared. For
the supplying cache, this designation is done automatically when the cache is snooped by
another cache. For the receiving cache, the designation is accomplished by asserting
MWB/WT#.
5.1.1.1.11. Read For Ownership
Read For Ownership is when an 82496 Cache Controller/82491 Cache SRAM allocation
causes the cache line to go directly to [M] state. This occurs when a memory write miss cycle
is frozen in the memory cycle buffer and an allocation cycle is issued.
In some systems it is preferable to eliminate main memory accesses whenever possible to
circumvent slow memory. Here, the allocation is carried out from another cache using cache-
to-cache transfer. This transfer avoids writing and reading main memory, and puts the
allocated line into the [M] state using the DRCTM# input.
Data for the allocation can also come from main memory. This would be the case if the data
was not found in another cache, and the MBC wanted to skip the [E] state by asserting
DRCTM#.
Read for ownership uses MFRZ# for all write misses so that the write cycle does not access
main memory. The MBC must complete this 'dummy' write cycle on the memory bus by
providing the cycle progress signals (Le., KWEND#, SWEND#, and CRDY#) to the 82496
Cache Controller. The subsequent allocation cycle is brought from memory, or from another
cache. Since write data is not updated in main memory, the line must be marked in the
modified state and all other caches must invalidate that line. If the line originates from another
cache, that cache must invalidate its copy. In this way the other cache transfers ownership.
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