82496 Cache Controller/82491 Cache Sram Optimized Interface; Memory Bus Interface; Snooping Logic; Pentium™ Processor Signals Latched In The 82496 Cache Controller And 82491 Cache Sram - Intel 82496 CACHE CONTROLLER User Manual

CACHE ARCHITECTURE OVERVIEW
Table 2-2. Pentium™ Processor Signals Latched in the 82496 Cache Controller and 82491
CacheSRAM
Pentium™ Processor Outputs 82491 cache SRAM Outputs 82496 Cache Controller Outputs
BE[7:0]# MBE#
CACHE CCACHE#
PCD CPCD
PWT CPWT
SCYC CSCYC
2.5. 82496 CACHE CONTROLLER/82491 CACHE SRAM
OPTIMIZED INTERFACE
The 82496 Cache Controller/82491 Cache SRAM interface is the connection between 82496
Cache Controller and 82491 Cache SRAM. Like the CPU bus interface, this optimized
interface is designed to provide the highest speed goal between the devices; therefore,
reference layouts and 'flight-time' specifications should be strictly adhered to.
2.6. MEMORY BUS INTERFACE
The Memory Bus Controller (MBC) is the interface logic required to control the Pentium
processor/82496 Cache Controller/82491 Cache SRAM and connect it to the memory bus and
rest of the system. The MBC may be simple enough to support a single-CPU write-through
cache, or complex enough to support a multiprocessing cache with external tags. The 82496
Cache Controller/82491 Cache SRAM is a very flexible chipset. The MBC determines exactly
how the 82496 Cache Controller/82491 Cache SRAM will work in a system.
An MBC consists of a few basic blocks: a snoop logic block, a memory bus cycle control
block (with synchronizers if necessary), and a clock cycle control block. The snoop block must
be able to communicate with the other caches when snooping is necessary. At the same time,
the cycle control blocks must interface to some arbitration logic external address and/or data
buffers.
2.6.1. Snooping LogiC
The MBC snooping logic is responsible for initiating a snoop in the 82496 Cache Controller
and providing the snoop response to the rest of the system. Snoop logic must also delay snoop
initiation if the 82496 Cache Controller is not capable of responding to a snoop.
When the master 82496 Cache Controller begins a cycle on the bus, all other caches snoop.
Once all the snoop results are returned to the master 82496 Cache Controller MBC, its snoop
logic must recognize the result and alter the cycle appropriately. The MBC may abort the
current cycle in memory, delay the cycle until a write-back is performed, or change the master
82496 Cache Controller's tag state according to the snoop information.
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