Intel 82496 CACHE CONTROLLER User Manual page 34

PINOUTS
Tables 1-4 through 1-9 list the signals which comprise each interface - both external (i.e. to
the memory bus controller) and internal (i.e. the Pentium processor CPU-Cache Chip Set
optimized interface).
Figure 1-7 illustrates signal partitioning.
Table 1-10 describes all Pentium processor signals to which the Memory Bus Controller has
access, all 82496 Cache Controller signals, all 82491 Cache SRAM signals, and all Optimized
interface signals.
Tables 1-11 to 1-13 list the Pentium processor CPU-Cache Chip Set signals which have
internal pull-up or pull-down resistors and are glitch free.
Table 1-14 lists the interconnects between the optimized interface signals.
Tables 1-15 to 1-18 list pin states at reset, Output pins, Input pins, and Input/Output pins.
The following abbreviations may be used in Tables 1-7 through 1-18: P (Pentium processor),
CC (82496 Cache Controller), and CS (82491 Cache SRAM).
For detailed Pentium processor pin descriptions, refer to the Pentium™ Processor Data Book.
For detailed 82496 Cache Controller and 82491 Cache SRAM pin descriptions refer to the
Hardware Interface chapter. Note that all input pins must meet their AC/DC specifications
to guarantee proper functional behavior of the 82496 Cache Controller and 82491 Cache
SRAM.
I
1-13