Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet
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Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet

Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet

Express chipset for the intel 82925x/82925xe memory controller hub (mch)
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®
Intel
925X/925XE Express
Chipset
Datasheet
®
For the Intel
82925X/82925XE Memory Controller Hub (MCH)
November 2004
Document Number:
301464-003

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Summary of Contents for Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU

  • Page 1 ® Intel 925X/925XE Express Chipset Datasheet ® For the Intel 82925X/82925XE Memory Controller Hub (MCH) November 2004 Document Number: 301464-003...
  • Page 2 Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Ω Look for systems with the Intel® Pentium® 4 Processor with HT Technology logo and also including an Intel® 925, 915, or 910 Express Chipset (see the product spec sheet or ask your salesperson).

  • Page 3: Table Of Contents

    3.3.3 Primary PCI and Downstream Configuration Mechanism ....39 3.3.4 PCI Express* Enhanced Configuration Mechanism ......40 ® 3.3.5 Intel 82925X/925XE MCH Configuration Cycle Flowchart ....42 I/O Mapped Registers ..................43 3.4.1 CONFIG_ADDRESS—Configuration Address Register ...... 43 3.4.2 CONFIG_DATA—Configuration Data Register ........44 Host Bridge/DRAM Controller Registers (D0:F0) .............
  • Page 4 PCIEXBAR—PCI Express* Register Range Base Address (D0:F0) ... 56 4.1.15 DMIBAR—Root Complex Register Range Base Address (D0:F0) ..57 4.1.16 DEVEN—Device Enable (D0:F0) ............58 ® 4.1.17 DEAP—DRAM Error Address Pointer (D0:F0) (Intel 82925X Only)... 59 ® 4.1.18 DERRSYN—DRAM Error Syndrome (D0:F0) (Intel 82925X Only) ..60 ®...
  • Page 5 PMLIMIT1—Prefetchable Memory Limit Address (D1:F0) ....124 8.1.19 CAPPTR1—Capabilities Pointer (D1:F0) ........... 124 8.1.20 INTRLINE1—Interrupt Line (D1:F0) ........... 125 8.1.21 INTRPIN1—Interrupt Pin (D1:F0) ............125 8.1.22 BCTRL1—Bridge Control (D1:F0) ............126 8.1.23 PM_CAPID1—Power Management Capabilities (D1:F0) ....128 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 6 ISA Hole (15 MB–16 MB) ..............162 9.2.2 TSEG ....................163 9.2.3 Pre-allocated Memory................. 163 PCI Memory Address Range (TOLUD – 4 GB) ..........163 9.3.1 APIC Configuration Space (FEC0_0000h–FECF_FFFFh)....164 9.3.2 HSEG (FEDA_0000h–FEDB_FFFFh) ..........165 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 7 Electrical Characteristics....................185 11.1 Absolute Maximum Ratings................185 11.2 Power Characteristics ..................186 11.3 Signal Groups..................... 187 11.4 General DC Characteristics ................189 Ballout and Package Information ..................193 12.1 Ballout......................... 193 12.2 Package Information ..................219 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 8 Testability ........................221 13.1 Complimentary Pins ................... 221 13.2 XOR Test Mode Initialization................222 13.3 XOR Chain Definition ..................222 13.4 XOR Chains......................222 13.5 Pads Excluded from XOR Mode(s) ..............242 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 9 ® Figure 2-1. Intel 82925X/82925XE MCH Signal Interface Diagram........ 22 ® Figure 3-1. Conceptual Intel 925X/925XE Express Chipset Platform PCI Configuration Diagram....................37 Figure 3-2. DMI Type 0 Configuration Address Translation ..........39 Figure 3-3. DMI Type 1 Configuration Address Translation ..........40 Figure 3-4.
  • Page 10 Table 13-8. XOR Chain #5....................233 Table 13-9. XOR Chain #6....................235 Table 13-10. XOR Chain #7.................... 237 Table 13-11. XOR Chain #8.................... 239 Table 13-12. XOR Chain #9.................... 241 Table 13-13. XOR Pad Exclusion List................242 ® Intel 82925X/82925XE MCH Datasheet...

  • Page 11: Revision History

    Revision Description Date • Initial Release -001 June 2004 • Added Intel ® ® -002 Extended Memory 64 Technology (Intel EM64T) August 2004 Support Information • Added 82925XE MCH Product Information -003 November 2004 § ® Intel 82925X/82925XE MCH Datasheet...
  • Page 12 Intel EM64T PCI Express Graphics Interface DMI Interface ⎯ One x16 PCI Express port ⎯ A chip-to-chip connection interface to Intel ® ⎯ Compatible with the PCI Express Base ICH6 ⎯ 2 GB/s point-to-point DMI to ICH6 (1 GB/s Specification Revision 1.0a...

  • Page 13: Introduction

    EM64T) enabling 64-bit memory addressability. Select versions of the Pentium 4 processor support Intel EM64T) as an enhancement to Intel's IA-32 architecture on workstation platforms. This enhancement enables the processor to execute operating systems and applications written to take advantage of Intel EM64T. Further details on the 64-bit extension architecture and programming ®...

  • Page 14: Figure 1-1. Intel 925X/925Xe Express Chipset System Block Diagram Example

    Introduction ® Figure 1-1. Intel 925X/925XE Express Chipset System Block Diagram Example ® ® Intel Pentium Processor 200/266 MHz FSB (800/1066 MT/s) ® Intel 925X/925XE Express Chipset System Memory DDR2 Channel A ® PCI Express Intel 82925X MCH/ DDR2 x16 Graphics ®...

  • Page 15: Terminology

    A second generation Double Data Rate SDRAM memory technology. DDR2 ® The Direct Media Interface is the connection between the MCH and the Intel ICH6. Front Side Bus. The FSB is synonymous with Host or processor bus Full reset is when PWROK is de-asserted. Warm reset is when both RSTIN# and Full Reset PWROK are asserted.

  • Page 16: Reference Documents

    Introduction Reference Documents Document Title Document Number/Location ® Intel 925X/925XE Express Chipset Thermal Design Guide http://intel.com/design/chipsets/ designex/301466.htm ® Intel I/O Controller Hub 6 (ICH6) Family Datasheet http://intel.com/design/chipsets/ datashts/301473.htm Advanced Configuration and Power Interface Specification, Version 2.0 http://www.acpi.info/ Advanced Configuration and Power Interface Specification, Version http://www.acpi.info/...

  • Page 17: System Memory Interface

    The MCH supports a memory thermal management scheme to selectively manage reads and/or writes. Memory thermal management can be triggered either by on-die thermal sensor, or by preset limits. Management limits are determined by weighted sum of various commands that are scheduled on the memory interface. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 18: Direct Media Interface (Dmi)

    • 100 MHz reference clock (shared with PCI Express Graphics Attach). • 32-bit downstream addressing • APIC and MSI interrupt messaging support. Will send Intel-defined “End Of Interrupt” broadcast message when initiated by the processor. • Message Signaled Interrupt (MSI) messages •...

  • Page 19: System Interrupts

    The MCH interrupt support includes: • Supports both 8259 and Pentium 4 processor FSB interrupt delivery mechanisms. • Supports interrupts signaled as upstream Memory Writes from PCI Express and DMI ⎯ MSIs routed directly to FSB ⎯ From I/OxAPICs ® Intel 82925X/82925XE MCH Datasheet...

  • Page 20: Mch Clocking

    • Supports processor states: C0, C1, C2, C3, and C4 • Supports System states: S0, S1, S3, S4, and S5 • Supports processor Thermal Management 2 (TM2) • Microsoft Windows NT* Hardware Design Guide v1.0 compliant § ® Intel 82925X/82925XE MCH Datasheet...

  • Page 21: Signal Description

    Stub Series Termination Logic. These are 1.8 V output capable buffers; 1.8 V tolerant. An I/O voltage of 1.9 V is needed for D DR2 533 MHz CL3-3-3. Analog reference or output. May be used as a threshold voltage or for buffer compensation. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 22: Figure 2-1. Intel ® 82925X/82925Xe Mch Signal Interface Diagram

    SWE_B# DDR2 SDQ_B[63:0] Channel SDM_B[7:0] SCB_B[7:0] SDQS_B[8:0], SDQS_B[8:0]# SCKE_B[3:0] SCLK_B[5:0], SCLK_B[5:0]# SODT_B[3:0] Note: ® 1. SCB_A[7:0] and SCB_B[7:0] are on the Intel 82925X only. 2. SDQS_A8/SDQS_A8# and SDQS_B8/SDQS_B8# are on the Intel® 82925X only. Signal_Info ® Intel 82925X/82925XE MCH Datasheet...

  • Page 23: Host Interface Signals

    Note that the Intel ICH6 must provide processor frequency select strap set- up and hold times around HCPURST#. This requires strict synchronization between MCH HCPURST# de-assertion and the Intel® ICH6 driving the straps. HDBSY# Data Bus Busy: This signal is used by the data bus owner to hold the data bus for transfers requiring more than one cycle.
  • Page 24 Asserted by the requesting agent during both halves of Request Phase. The same information is provided in both halves of the request phase. ® Intel 82925X/82925XE MCH Datasheet...
  • Page 25 Host Voltage Swing: This signal provides the reference voltage used by FSB RCOMP circuits. HSWING is used for the signals handled by HRCOMP. HVREF Host Reference Voltage Reference: Voltage input for the data, address, and common clock signals of the Host GTL interface. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 26: Ddr2 Dram Channel A Interface

    SDRAM are masked. There is one SDM_Ax signal for every data byte lane. SCB_A[7:0] ECC Check Byte: These signals require a 6-layer board to be routed. ® (Intel 82925X SSTL-1.8 Only) SDQS_A[8:0] Data Strobes: For DDR2, SDQS_Ax and its complement SDQS_Ax# (82925X MCH) SSTL-1.8...

  • Page 27: Ddr2 Dram Channel B Interface

    SDRAM are masked. There is one SDM_Bx signal for every data byte lane. SCB_B[7:0] ECC Check Byte: These signals require a 6-layer board to be routed. ® (Intel 82925X SSTL-1.8 Only) SDQS_B[8:0] Data Strobes: For DDR2, SDQS_Bx and its complement SDQS_Bx# (82925X MCH) SSTL-1.8...

  • Page 28: Ddr2 Dram Reference And Compensation

    Normal Lane Ball Operation Reversed EXP_TXP0 EXP_TXP15 EXP_TXP1 EXP_TXP14 … … … EXP_TXP14… EXP_TXP1… EXP_TXP15 EXP_TXP0 0 = MCH’s PCI Express lane numbers are reversed 1 = Normal operation ® Intel 82925X/82925XE MCH Datasheet...

  • Page 29: Clocks, Reset, And Miscellaneous

    CMOS RSTIN# Reset In: When asserted, this signal will asynchronously reset the MCH ® logic. This signal is connected to the PLTRST# output of the Intel ICH6. HVIN All PCI Express Graphics Attach output signals will also tri-state compatible with PCI Express* Specification Rev 1.0a.

  • Page 30: Power And Ground

    ISO: Isolate input buffer so that it does not oscillate if input left floating TRI: Tri-state Weak internal pull-up Weak internal pull-down STRAP: Strap input sampled during assertion or on the de-asserting edge of RSTIN# ® Intel 82925X/82925XE MCH Datasheet...

  • Page 31: Table 2-1. Host Interface Reset And S3 States

    TRI (No VTT) HBREQ0# TERM HV TERM HV TRI (No VTT) HPCREQ# TERM HV TERM HV TRI (No VTT) HVREF 20 Ω resistor HRCOMP TRI after RCOMP for board with target impedance of 60 Ω HSWING HSCOMP ® Intel 82925X/82925XE MCH Datasheet...

  • Page 32: Table 2-2. System Memory Reset And S3 States

    SCLK_A[5:0]# SCS_A[3:0]# SMA_A[13:0] SBS_A[2:0] SRAS_A# SCAS_A# SWE_A# SDQ_A[63:0] SDM_A[7:0] SCB_A[7:0] SDQS_A[8:0] SDQS_A[8:0]# SCKE_A[3:0] SODT_A[3:0] System Channel B Memory SCLK_B[5:0] SCLK_B[5:0]# SCS_B[3:0]# SMA_B[13] SMA_B[12:11] SMA_B[10:8] SMA_B[7] SMA_B[6:0] SBS_B[2] SBS_B[1:0] SRAS_B# SCAS_B# SWE_B# SDQ_B[63:0] SDM_B[7:0] SCB_B[7:0] SDQS_B[8:0] ® Intel 82925X/82925XE MCH Datasheet...

  • Page 33: Table 2-3. Pci Express* Graphics X16 Port Reset And S3 States

    Interface Signal Name RSTIN# De-assertion down Assertion DMI_RXN[3:0] CMCT CMCT CMCT DMI_RXP[3:0] CMCT CMCT CMCT DMI_TXN[3:0] CMCT 1.0 V CMCT 1.0 V CMCT 1.0 V DMI_TXP[3:0] CMCT 1.0 V CMCT 1.0 V CMCT 1.0 V ® Intel 82925X/82925XE MCH Datasheet...

  • Page 34: Table 2-5. Clocking Reset And S3 States

    Table 2-6. Miscellaneous Reset and S3 States State During State After RSTIN# Pull-up/ Interface Signal Name RSTIN# De-assertion Pull-down Assertion RSTIN# Misc. PWROK EXTTS# BSEL[2:0] MTYPE TERM HV TERM HV TERM HV EXP_SLR TERM HV TERM HV TERM HV ICH_SYNC# § ® Intel 82925X/82925XE MCH Datasheet...

  • Page 35: Register Description

    Read / Write / Sticky bit(s). These bits can be read and written. Bits are not cleared by "warm" reset, but will be reset with a cold/complete reset (for PCI Express related bits a cold reset is “Power Good Reset” as defined in the PCI Express* Specification). ® Intel 82925X/82925XE MCH Datasheet...
  • Page 36 In addition to reserved bits within a register, the MCH contains address locations in the Registers configuration space of the Host Bridge entity that are marked either "Reserved" or “Intel Reserved”. The MCH responds to accesses to “Reserved” address locations by completing the host cycle.

  • Page 37: Platform Configuration

    PCI bus behind a PCI-to-PCI bridge that is a device resident on PCI bus 0. Note: A physical PCI bus 0 does not exist and that DMI and the internal devices in the MCH and Intel ICH6 logically constitute PCI Bus 0 to configuration software. This is shown in Figure 3-1.

  • Page 38: General Routing Configuration Accesses

    Configuration cycles to the Intel ICH6 internal devices and Primary PCI (including downstream devices) are routed to the Intel ICH6 via DMI. Configuration cycles to both the PCI Express Graphics PCI compatibility configuration space and the PCI Express Graphics extended configuration space are routed to the PCI Express Graphics port.

  • Page 39: Logical Pci Bus 0 Configuration Mechanism

    Device 0 on PCI Bus 0. The Host-PCI Express Bridge entity within the MCH is hardwired as Device 1 on PCI Bus 0. The Intel ICH6 decodes the Type 0 access and generates a configuration access to the selected internal device.

  • Page 40: Pci Express* Enhanced Configuration Mechanism

    Function Number and Register Address fields to provide indexing into the 4 KB of configuration space allocated to each potential device. For PCI Compatible Configuration Requests, the Extended Register Address field must be all zeros. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 41: Figure 3-4. Memory Map To Pci Express* Device Configuration Space

    PCI Express* x16 Graphics Interface or DMI pins (i.e., translated to configuration writes). See the PCI Express Specification for more information on both the PCI 2.3 compatible and PCI Express enhanced configuration mechanism and transaction rules. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 42: Intel 82925X/925Xe Mch Configuration Cycle Flowchart

    Register Description ® 3.3.5 Intel 82925X/925XE MCH Configuration Cycle Flowchart ® Figure 3-5. Intel 82925X/82925XE MCH Configuration Cycle Flowchart DW I/O Write to CONFIG_ADDRES S with bit 31 = 1 I/O Read/Write to CONFIG_DATA Bus# = 0 MCH Generates Bus# > Sec Bus...

  • Page 43: I/O Mapped Registers

    PCI Express Graphics. This field is mapped to byte 8 [7:0] of the request header format during PCI Express Configuration cycles and A[23:16] during the DMI Type 1 configuration cycles. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 44: Config_Data-Configuration Data Register

    Configuration Data Window (CDW): If bit 31 of CONFIG_ADDRESS is 1, any 0000 0000h I/O access to the CONFIG_DATA register will produce a configuration transaction using the contents of CONFIG_ADDRESS to determine the bus, device, function, and offset of the register to be accessed. § ® Intel 82925X/82925XE MCH Datasheet...

  • Page 45: Host Bridge/Dram Controller Registers (D0:F0)

    40h–43h EPBAR Egress Port Base Address 00000000h 44h–47h MCHBAR MCH Memory Mapped Register Range Base 00000000h Address 48h–4Bh PCIEXBAR PCI Express* Register Range Base Address E0000000h 4Ch–4Fh DMIBAR Root Complex Register Range Base Address 00000000h ® Intel 82925X/82925XE MCH Datasheet...
  • Page 46 Channel A DRAM Rank Boundary Address 1 102h C0DRB2 Channel A DRAM Rank Boundary Address 2 103h C0DRB3 Channel A DRAM Rank Boundary Address 3 104h–107h — Reserved — — 108h C0DRA0 Channel A DRAM Rank 0,1 Attribute ® Intel 82925X/82925XE MCH Datasheet...
  • Page 47 R/W, RO 195h–19Fh — Reserved — — 1A0h–1A3h C1DRC0 Channel B DRAM Controller Mode 0 00000000h R/W, RO 1A4h–F0Fh — Reserved — — F10h–F13h PMCFG Power Management Configuration 00000000h F14h PMSTS Power Management Status 00000000h R/W/C/S ® Intel 82925X/82925XE MCH Datasheet...

  • Page 48: Device 0 Function 0 Pci Configuration Register Details

    16 bits This register combined with the Device Identification register uniquely identifies any PCI device. Access & Description Default 15:0 Vendor Identification Number (VID): PCI standard identification for Intel. 8086h 4.1.2 DID—Device Identification (D0:F0) PCI Device: Address Offset: Default Value:...

  • Page 49: Pcicmd-Pci Command (D0:F0)

    Bus Master Enable (BME). The MCH is always enabled as a master. This bit is hardwired to a 1. Memory Access Enable (MAE). The MCH always allows access to main memory. This bit is not implemented and is hardwired to 1. I/O Access Enable (IOAE). Hardwired to a 0. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 50: Pcists-Pci Status (D0:F0)

    CAPPTR at configuration address offset 34h. Register CAPPTR contains an offset pointing to the start address within configuration space of this device where the Capability standard register resides. Reserved ® Intel 82925X/82925XE MCH Datasheet...

  • Page 51: Rid-Revision Identification (D0:F0)

    Access & Description Default Revision Identification Number (RID): This is an 8-bit value that indicates the ® revision identification number for the MCH Device 0. See Intel 925X/925XE Express Chipset Specification Update for the value of the Revision Identification Register. 4.1.6 CC—Class Code (D0:F0)

  • Page 52: Mlt-Master Latency Timer (D0:F0)

    Description Default 15:0 R/WO Subsystem Vendor ID (SUBVID): This field should be programmed during boot- 0000h up to indicate the vendor of the system board. After it has been written once, it becomes read only. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 53: Sid-Subsystem Identification (D0:F0)

    The CAPPTR provides the offset that is the pointer to the location of the first device capability in the capability list. Access & Description Default Pointer to the offset of the first capability ID register block: In this case the first capability is the product-specific Capability Identifier (CAPID0). ® Intel 82925X/82925XE MCH Datasheet...

  • Page 54: Epbar-Egress Port Base Address (D0:F0)

    This register ensures that a naturally aligned 4-KB space is allocated within total addressable memory space of 4 GB. System software uses this base address to program the MCH MMIO register set. 11:0 Reserved ® Intel 82925X/82925XE MCH Datasheet...

  • Page 55: Mchbar-Mch Memory Mapped Register Range Base Address (D0:F0)

    This register ensures that a naturally aligned 16-KB space is allocated within total addressable memory space of 4 GB. System software uses this base address to program the MCH Memory-mapped register set. 13:0 Reserved ® Intel 82925X/82925XE MCH Datasheet...

  • Page 56: Pciexbar-Pci Express* Register Range Base Address (D0:F0)

    + 0 * 4 KB = PCI Express Base Address + 32 KB. Remember that this address is the beginning of the 4-KB space that contains both the PCI compatible configuration space and the PCI Express extended configuration space. 27:0 Reserved ® Intel 82925X/82925XE MCH Datasheet...

  • Page 57: Dmibar-Root Complex Register Range Base Address (D0:F0)

    This register ensures that a naturally aligned 4-KB space is allocated within total addressable memory space of 4 GB. System software uses this base address to program the DMI register set. 11:0 Reserved ® Intel 82925X/82925XE MCH Datasheet...

  • Page 58: Deven-Device Enable (D0:F0)

    Express internal clock (lgclk) and asserts PCI Express internal reset (lgrstb). dependent 1 = Bus 0 Device 1 Function 0 is enabled and visible. Host Bridge: Bus 0 Device 0 Function 0 can not be disabled and is therefore hardwired to 1. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 59: Deap-Dram Error Address Pointer (D0:F0) (Intel 82925X Only)

    Host Bridge/DRAM Controller Registers (D0:F0) ® 4.1.17 DEAP—DRAM Error Address Pointer (D0:F0) (Intel 82925X Only) PCI Device: Address Offset: Default Value: 00000000h Access: RO/S Size: 32 bits This register contains the address of detected DRAM ECC error(s). Access & Description...

  • Page 60: Derrsyn-Dram Error Syndrome (D0:F0) (Intel 82925X Only)

    Host Bridge/DRAM Controller Registers (D0:F0) ® 4.1.18 DERRSYN—DRAM Error Syndrome (D0:F0) (Intel 82925X Only) PCI Device: Address Offset: Default Value: Access: RO/S Size: 8 bits This register is used to report the ECC syndromes for each quad word of a 32B-aligned data quantity read from the DRAM array.

  • Page 61: Derrdst-Dram Error Destination (D0:F0) (Intel

    Host Bridge/DRAM Controller Registers (D0:F0) ® 4.1.19 DERRDST—DRAM Error Destination (D0:F0) (Intel 82925X Only) PCI Device: Address Offset: Default Value: Access: RO/S Size: 8 bits This register is used to report the destination of the data containing an ECC error whose address is recorded in DEAP register.

  • Page 62: Pam0-Programmable Attribute Map 0 (D0:F0)

    PAM regions: At the time that a DMI or PCI Express graphics attach accesses to the PAM region may occur, the targeted PAM segment must be programmed to be both readable and writeable. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 63: Pam1-Programmable Attribute Map 1 (D0:F0)

    01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 64: Pam2-Programmable Attribute Map 2 (D0:F0)

    01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 65: Pam3-Programmable Attribute Map 3 (D0:F0)

    01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 66: Pam4-Programmable Attribute Map 4 (D0:F0)

    01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 67: Pam5-Programmable Attribute Map 5 (D0:F0)

    01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 68: Pam6-Programmable Attribute Map 6 (D0:F0)

    01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI. 10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11 = Normal DRAM Operation: All reads and writes are serviced by DRAM. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 69: Lac-Legacy Access Control (D0:F0)

    All References to MDA and VGA space are routed to the DMI Illegal combination All VGA and MDA references are routed to PCI Express Graphics Attach. All VGA references are routed to PCI Express Graphics Attach. MDA references are routed to the ® Intel 82925X/82925XE MCH Datasheet...

  • Page 70: Tolud-Top Of Low Usable Dram (D0:F0)

    The host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register. If this register is set to 0000 0b, it implies 128 MBs of system memory. Reserved ® Intel 82925X/82925XE MCH Datasheet...

  • Page 71: Smram-System Management Ram Control (D0:F0)

    SMM space, otherwise the access is forwarded to DMI. Since the MCH supports only the SMM space between A0000h and BFFFFh, this field is hardwired to 010. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 72: Esmramc-Extended System Management Ram Control (D0:F0)

    ERRCMD and PCICMD registers). These bits are set regardless of whether or not the SERR is enabled and generated. After the error processing is complete, the error logging mechanism can be unlocked by clearing the appropriate status bit by software writing a 1 to it. ® Intel 82925X/82925XE MCH Datasheet...
  • Page 73 1. A multiple bit error that occurs after this bit is set will overwrite the EAP, CN, and DN fields with the multiple-bit error signature and the MEF bit will also be set. This bit is reset on PWROK. 82925XE MCH Reserved ® Intel 82925X/82925XE MCH Datasheet...

  • Page 74: Errcmd-Error Command (D0:F0)

    This register controls the MCH responses to various system errors. Since the MCH does not have an SERR# signal, SERR messages are passed from the MCH to the Intel ICH6 over DMI. When a bit in this register is set, a SERR message will be generated on DMI when the corresponding flag is set in the ERRSTS register.

  • Page 75: Smicmd-Smi Command (D0:F0)

    1 = The MCH generates an SMI DMI special cycle when the DRAM controller detects a single bit error. 0 = Reporting of this condition via SMI messaging is disabled. For systems that do not support ECC, this bit must be disabled. 82925XE MCH Reserved ® Intel 82925X/82925XE MCH Datasheet...

  • Page 76: Scicmd-Sci Command (D0:F0)

    This register holds 32 writable bits with no functionality behind them. It is for the convenience of BIOS and graphics drivers. Access & Description Default 31:0 Scratchpad Data: 1 DWord of data storage. 00000000 h ® Intel 82925X/82925XE MCH Datasheet...

  • Page 77: Capid0-Capability Identifier (D0:F0)

    Next Capability Pointer: This field is hardwired to 00h indicating the end of the capabilities linked list. CAP_ID: This field has the value 1001b to identify the CAP_ID assigned by the PCI SIG for vendor dependent capability pointers. § ® Intel 82925X/82925XE MCH Datasheet...
  • Page 78 Host Bridge/DRAM Controller Registers (D0:F0) ® Intel 82925X/82925XE MCH Datasheet...

  • Page 79: Mchbar Registers

    18Ch C1DCLKDIS Channel B DRAM Clock Disable 18Dh — Reserved — — 18E–18Fh C1BNKARC Channel B Bank Architecture 0000h 190–193h — Reserved — — 194h C1DRT1 Channel B DRAM Timing Register 1 900122h R/W, RO ® Intel 82925X/82925XE MCH Datasheet...

  • Page 80: Mchbar Register Details

    (256 Mbit, 512 Mbit, or 1 Gbit) and the x8 or x16 configuration. With independent channels, a value of 01h in C0DRB0 indicates that 32 MB of DRAM has been populated in the first rank, and the top address in that rank is 32 MB. ® Intel 82925X/82925XE MCH Datasheet...
  • Page 81 Address 31:27 to determine the upper address limit of a particular rank. Bits 1:0 must be 0s. Bit 7 may be programmed to a 1 in the highest DRB (DRB3) if 4 GB of memory is present. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 82: C0Drb1-Channel A Dram Rank Boundary Address 1

    The operation of this register is detailed in the description for register C0DRB0. 5.1.4 C0DRB3—Channel A DRAM Rank Boundary Address 3 MMIO Range: MCHBAR Address Offset: 103h Default Value: Access: Size: 8 bits The operation of this register is detailed in the description for register C0DRB0. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 83: C0Dra0-Channel A Dram Rank 0,1 Attribute

    Others = Reserved 5.1.6 C0DRA2—Channel A DRAM Rank 2,3 Attribute MMIO Range: MCHBAR Address Offset: 109h Default Value: Access: Size: 8 bits The operation of this register is detailed in the description for register C0DRA0. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 84: C0Dclkdis-Channel A Dram Clock Disable

    Note: Since there are multiple clock signals assigned to each Rank of a DIMM, it is important to clarify exactly which Rank width field affects which clock signal: Channel Rank Clocks Affected 0 or 1 SCLK_A[2:0]/ SCLK_A[2:0]# 2 or 3 SCLK_A[5:3]/ SCLK_A[5:3]# 0 or 1 SCLK_B[2:0]/ SCLK_B[2:0]# 2 or 3 SCLK_B[5:3]/ SCLK_B[5:3]# ® Intel 82925X/82925XE MCH Datasheet...

  • Page 85: C0Bnkarc-Channel A Dram Bank Architecture

    01 = 8 Bank. 1X = Reserved Rank 1 Bank Architecture 00 = 4 Bank. 01 = 8 Bank. 1X = Reserved Rank 0 Bank Architecture 00 = 4 Bank. 01 = 8 Bank. 1X = Reserved ® Intel 82925X/82925XE MCH Datasheet...

  • Page 86: C0Drt1-Channel A Dram Timing Register

    RAS-MAX 18:10 Reserved CASB Latency (tCL). This value is programmable on DDR2 DIMMs. The value programmed here must match the CAS Latency of every DDR2 DIMM in the system. Encoding DDR2 CL Reserved Reserved ® Intel 82925X/82925XE MCH Datasheet...
  • Page 87 000 = 2 DRAM clocks 001 = Reserved 010 = 4 DRAM clocks 011 = 5 DRAM clocks 100 – 111 = Reserved ® Intel 82925X/82925XE MCH Datasheet...

  • Page 88: C0Drc0-Channel A Dram Controller Mode 0

    010 = Refresh enabled. Refresh interval 7.8 µsec 011 = Refresh enabled. Refresh interval 3.9 µsec 100 = Refresh enabled. Refresh interval 1.95 µsec 111 = Refresh enabled. Refresh interval 64 clocks (fast refresh mode) Other = Reserved Reserved ® Intel 82925X/82925XE MCH Datasheet...
  • Page 89 DRAM Type (DT). This field is used to select between supported SDRAM types. This bit is controlled by the MTYPE strap signal. 00 = Reserved 01 = Reserved 10 = Second Revision Dual Data Rate (DDR2) SDRAM 11 = Reserved ® Intel 82925X/82925XE MCH Datasheet...

  • Page 90: C1Drb0-Channel B Dram Rank Boundary Address 0

    The operation of this register is detailed in the description for register C0DRB0. 5.1.15 C1DRA0—Channel B DRAM Rank 0,1 Attribute MMIO Range: MCHBAR Address Offset: 188h Default Value: Access: Size: 8 bits The operation of this register is detailed in the description for register C0DRA0. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 91: C1Dra2-Channel B Dram Rank 2,3 Attribute

    The operation of this register is detailed in the description for register C0DRT1. 5.1.20 C1DRC0—Channel B DRAM Controller Mode 0 MMIO Range: MCHBAR Address Offset: 1A0h Default Value: 00000000h Access: Size: 32 bits The operation of this register is detailed in the description for register C0DRC0. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 92: Pmcfg-Power Management Configuration

    A self refresh exit sequence initiated by a power management exit. It is cleared by the BIOS in a warm reset (Reset# asserted while PWOK is asserted) exit sequence. 0 = Channel A not guaranteed to be in self-refresh. 1 = Channel A in Self-Refresh. § ® Intel 82925X/82925XE MCH Datasheet...

  • Page 93: Epbar Registers-Egress Port Register Summary

    (Type 1) Link #1 (Type 0) Egress Port Main Memory (Port #0) Subsystem Link #2 (Type 0) Link #1 (Type 0) (Port #1) Link #1 (Type 0) ® Intel ICH6 Egress Port (Port #0) Egress_LinkDeclar_Topo ® Intel 82925X/82925XE MCH Datasheet...

  • Page 94: Epesd-Ep Element Self Description

    Element Self Description. This field reports 2 (one each for PCI Express* x16 Graphics Interface and DMI). Reserved Element Type: This field Indicates the type of the Root Complex Element. 1h = Port to system memory ® Intel 82925X/82925XE MCH Datasheet...

  • Page 95: Eple1D-Ep Link Entry 1 Description

    Root Complex Element. Access & Description Default 63:32 Reserved 31:12 R/WO Link Address: This field provides the memory-mapped base address of the 0 0000h RCRB that is the target element (DMI) for this link entry. 11:0 Reserved ® Intel 82925X/82925XE MCH Datasheet...

  • Page 96: Eple2D-Ep Link Entry 2 Description

    The link address specifies the configuration address (segment, bus, device, function) of the target root port. R/WO Link Valid 0 = Link Entry is not valid and will be ignored. 1 = Link Entry specifies a valid link. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 97: Eple2A-Ep Link Entry 2 Address

    Root Complex Element. Access & Description Default 63:28 Reserved 27:20 Bus Number 19:15 Device Number: Target for this link is PCI Express* x16 port (Device 1). 0 0001b 14:12 Function Number 000b 11:0 Reserved § ® Intel 82925X/82925XE MCH Datasheet...
  • Page 98 EPBAR Registers—Egress Port Register Summary ® Intel 82925X/82925XE MCH Datasheet...

  • Page 99: Dmibar Registers-Direct Media Interface (Dmi) Rcrb

    DMIBAR Registers—Direct Media Interface (DMI) RCRB This Root Complex Register Block (RCRB) controls the MCH-Intel ICH6 serial interconnect. The base address of this space is programmed in DMIBAR in device 0 configuration space. These registers are offset from the DMIBAR base address Table 7-1.

  • Page 100: Direct Media Interface (Dmi) Rcrb Register Details

    Low Priority Extended VC Count (LPEVC): This field indicates that there are 000b no additional VCs of low priority with extended capabilities. Reserved R/WO Extended VC Count: This field indicates that there is one additional VC (VC1) 001b that exists with extended capabilities. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 101: Dmipvccap2-Dmi Port Vc Capability Register 2

    Load VC Arbitration Table (LAT): This field indicates that the table programmed should be loaded into the VC arbitration table. This bit is defined as read/write with always returning 0 on reads. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 102: Dmivc0Rcap-Dmi Vc0 Resource Capability

    Reject Snoop Transactions (RTS): This VC must be able to take snoopable transactions. Advanced Packet Switching (APS): This VC is capable of all transactions, not just advanced packet switching transactions. 13:8 Reserved Port Arbitration Capability (PAC): This field indicates that this VC uses fixed port arbitration. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 103: Dmivc0Rctl0-Dmi Vc0 Resource Control

    Reserved Transaction Class / Virtual Channel Map (TVM): This field indicates which transaction classes are mapped to this virtual channel. When a bit is set, this transaction class is mapped to the virtual channel. Reserved ® Intel 82925X/82925XE MCH Datasheet...

  • Page 104: Dmivc0Rsts-Dmi Vc0 Resource Status

    Advanced Packet Switching (APS): This VC is capable of all transactions, not just advanced packet switching transactions. 13:8 Reserved Port Arbitration Capability (PAC): This field indicates the port arbitration capability is time-based WRR of 128 phases. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 105: Dmivc1Rctl1-Dmi Vc1 Resource Control

    Reserved Transaction Class / Virtual Channel Map (TVM): This field indicates which transaction classes are mapped to this virtual channel. When a bit is set, this transaction class is mapped to the virtual channel. Reserved ® Intel 82925X/82925XE MCH Datasheet...

  • Page 106: Dmivc1Rsts-Dmi Vc1 Resource Status

    Active State Link PM Support (APMS): This field indicates that L0s is supported on DMI. Maximum Link Width (MLW): This field indicates the maximum link width is 4 ports. Maximum Link Speed (MLS): This field indicates the link speed is 2.5 Gb/s. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 107: Dmilctl-Dmi Link Control

    Negotiated Link Width (NLW): This field is valid only when the link is in the L0, L0s, or L1 states (after link width negotiation is successfully completed). Negotiated link width is x4 (000100b). All other encodings are reserved. Link Speed (LS) Link is 2.5 Gb/s. § ® Intel 82925X/82925XE MCH Datasheet...
  • Page 108 DMIBAR Registers—Direct Media Interface (DMI) RCRB ® Intel 82925X/82925XE MCH Datasheet...

  • Page 109: Host-Pci Express* Graphics Bridge Registers (D1:F0)

    Revision Identification See Register Description 09–0Bh Class Code 060400h Cache Line Size — Reserved — — HDR1 Header Type 0F–17h — Reserved — — PBUSN1 Primary Bus Number SBUSN1 Secondary Bus Number SUBUSN1 Subordinate Bus Number ® Intel 82925X/82925XE MCH Datasheet...
  • Page 110 0000h AA–ABh DSTS Device Status 0000h AC–AFh LCAP Link Capabilities 02012E01h R/WO B0–B1h LCTL Link Control 0000h RO, R/W B2–B3h LSTS Link Status 1001h B4–B7h SLOTCAP Slot Capabilities 00000000h R/WO B8–B9h SLOTCTL Slot Control 01C0h ® Intel 82925X/82925XE MCH Datasheet...
  • Page 111 00000000h RO, R/WO 154–157h — Reserved — — 158–15Fh LE1A Link Entry 1 Address 0000000000 R/WO 000000h 160–217h — Reserved — — 218–21Fh PEGSSTS PCI Express*-Graphics Sequence Status 0000000000 000FFFh 220–FFFh — Reserved — — ® Intel 82925X/82925XE MCH Datasheet...

  • Page 112: Device 1 Configuration Register Details

    Size: 16 bits This register combined with the Device Identification register uniquely identifies any PCI device. Access & Description Default 15:0 Vendor Identification (VID1): PCI standard identification for Intel. 8086h 8.1.2 DID1—Device Identification (D1:F0) PCI Device: Address Offset: Default Value:...

  • Page 113: Pcicmd1-Pci Command (D1:F0)

    The MCH communicates the SERRB condition by sending an SERR ® message to the Intel ICH6. This bit, when set, enables reporting of non-fatal and fatal errors to the Root Complex. Note that errors are reported if enabled either...

  • Page 114: Pcists1-Pci Status (D1:F0)

    Received Master Abort Status (RMAS): Not Applicable or Implemented. Hardwired to 0. The concept of a master abort does not exist on primary side of this device. ® Intel 82925X/82925XE MCH Datasheet...
  • Page 115 INTA Status: This field indicates that an interrupt message is pending internally to the device. Only PME and Hot Plug sources feed into this status bit (not PCI INTA-INTD assert and de-assert messages). The INTA Assertion Disable bit, PCICMD1[10], has no effect on this bit. Reserved ® Intel 82925X/82925XE MCH Datasheet...

  • Page 116: Rid1-Revision Identification (D1:F0)

    “stepped” through the manufacturing process. It is always the same as the RID values in all other devices in this ® component. See Intel 925X/925XE Express Chipset Specification Update for the value of the Revision Identification Register.

  • Page 117: Cl1-Cache Line Size (D1:F0)

    Since device 1 is an internal device and its primary bus is always 0, these bits are read only and are hardwired to 0. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 118: Sbusn1-Secondary Bus Number (D1:F0)

    1 bridge. When only a single PCI device resides on the PCI Express*-G segment, this register will contain the same value as the SBUSN1 register. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 119: Iobase1-I/O Base Address (D1:F0)

    I/O Address Limit (IOLIMIT): This field corresponds to A[15:12] of the I/O address limit of device 1. Devices between this upper limit and IOBASE1 will be passed to the PCI Express* hierarchy associated with this device. Reserved ® Intel 82925X/82925XE MCH Datasheet...

  • Page 120: Ssts1-Secondary Status (D1:F0)

    Note: This bit can only be set when the Parity Error Enable bit in the Bridge Control register is set. Fast Back-to-Back (FB2B): Hardwired to 0. Reserved 66/60 MHz capability (CAP66): Hardwired to 0. Reserved ® Intel 82925X/82925XE MCH Datasheet...

  • Page 121: Mbase1-Memory Base Address (D1:F0)

    1-MB boundary. Access & Description Default 15:4 Memory Address Base (MBASE): This field corresponds to A[31:20] of the FFFh lower limit of the memory range that will be passed to PCI Express*. Reserved ® Intel 82925X/82925XE MCH Datasheet...

  • Page 122: Mlimit1-Memory Limit Address (D1:F0)

    MCH hardware to enforce prevention of overlap and operations of the system in the case of overlap are not guaranteed. Access & Description Default 15:4 Memory Address Limit (MLIMIT): This field corresponds to A[31:20] of the 000h upper limit of the address range passed to PCI Express*. Reserved ® Intel 82925X/82925XE MCH Datasheet...

  • Page 123: Pmbase1-Prefetchable Memory Base Address (D1:F0)

    Prefetchable Memory Base Address (MBASE): This field corresponds to FFFh A[31:20] of the lower limit of the memory range that will be passed to PCI Express*. 64-bit Address Support: This field indicates that the bridge supports only 32 bit addresses. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 124: Pmlimit1-Prefetchable Memory Limit Address (D1:F0)

    The capabilities pointer provides the address offset to the location of the first entry in this device’s linked list of capabilities. Access & Description Default First Capability (CAPPTR1): The first capability in the list is the Subsystem ID and Subsystem Vendor ID Capability. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 125: Intrline1-Interrupt Line (D1:F0)

    8 bits This register specifies which interrupt pin this device uses. Access & Description Default Interrupt Pin: As a single function device, the PCI Express* device specifies INTA as its interrupt pin. 01h = INTA ® Intel 82925X/82925XE MCH Datasheet...

  • Page 126: Bctrl1-Bridge Control (D1:F0)

    1 = Execute 16-bit address decodes on VGA I/O accesses. VGA Enable (VGAEN): This bit controls the routing of processor-initiated transactions targeting VGA compatible I/O and memory address ranges. See the VGAEN/MDAP table in Device 0, offset 97h[0]. ® Intel 82925X/82925XE MCH Datasheet...
  • Page 127 MCH receives across the link (upstream) a Read Data Completion Poisoned TLP. 0 = Master Data Parity Error bit in Secondary Status register cannot be set. 1 = Master Data Parity Error bit in Secondary Status register can be set.. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 128: Pm_Capid1-Power Management Capabilities (D1:F0)

    MSICH (CAPL[0] @ 7Fh) is 1, then the next item in the capabilities list is the PCI Express* capability at A0h. Capability ID: Value of 01h identifies this linked list item (capability structure) as being for PCI Power Management registers. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 129: Pm_Cs1-Power Management Control/Status (D1:F0)

    MMR cycles in the D3 state. The device must return to the D0 state to be fully functional. There is no hardware functionality required to support these power states. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 130: Ss_Capid-Subsystem Id And Vendor Id Capabilities (D1:F0)

    15:0 R/WO Subsystem Vendor ID (SSVID): This field identifies the manufacturer of the 8086h subsystem and is the same as the vendor ID that is assigned by the PCI Special Interest Group. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 131: Msi_Capid-Message Signaled Interrupts Capability Id (D1:F0)

    Pointer to Next Capability: This field contains a pointer to the next item in the capabilities list that is the PCI Express* capability. Capability ID: 05h = Identifies this linked list item (capability structure) as being for MSI registers. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 132: Mc-Message Control (D1:F0)

    MSI Enable (MSIEN) Controls the ability of this device to generate MSIs. 0 = MSI will not be generated. 1 = MSI will be generated when we receive PME or HotPlug messages. INTA will not be generated and INTA Status (PCISTS1[3]) will not be set. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 133: Ma-Message Address (D1:F0)

    When the device must generate an interrupt request, it writes a 32-bit value to the memory address specified in the MA register. The upper 16 bits are always set to 0. This register supplies the lower 16 bits. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 134: Peg_Capl-Pci Express* Capability List (D1:F0)

    BIOS must initialize this field appropriately if a slot connection is not implemented. Device/Port Type: Hardwired to 0100 to indicate root port of PCI Express Root Complex. PCI Express Capability Version: Hardwired to 1 as it is the first version. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 135: Dcap-Device Capabilities (D1:F0)

    Extended Tag Field Supported: Hardwired to indicate support for 5-bit Tags as a Requestor. Phantom Functions Supported: Hardwired to 0. Max Payload Size: Hardwired to indicate 128B maximum supported payload for 000b Transaction Layer Packets (TLP). ® Intel 82925X/82925XE MCH Datasheet...

  • Page 136: Dctl-Device Control (D1:F0)

    Correctable Error Reporting Enable: 0 = Disable. 1 = Enable. Correctable errors will be reported. For a Root Port, the reporting of correctable errors is internal to the root. No external ERR_CORR message is generated. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 137: Dsts-Device Status (D1:F0)

    Correctable Error Detected bit CESTS device 1, offset 1D0h, Bit [0]. This will reduce the value of Receiver Error detection when L0s is enabled. Disable L0s for accurate Receiver Error reporting. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 138: Lcap-Link Capabilities (D1:F0)

    Active State Link PM Support: L0s and L1 entry supported. Max Link Width: Hardwired to indicate X16. When Force X1 mode is enabled on this PCI Express* x16 Graphics Interface device, this field reflects X1 (01h). Max Link Speed: Hardwired to indicate 2.5 Gb/s. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 139: Lctl-Link Control (D1:F0)

    Active State PM: This field controls the level of active state power management supported on the given link. 00 = Disabled 01 = L0s Entry Supported 10 = Reserved 11 = L0s and L1 Entry Supported ® Intel 82925X/82925XE MCH Datasheet...

  • Page 140: Lsts-Link Status (D1:F0)

    00h = Reserved 01h = X1 04h = Reserved 08h = Reserved 10h = X16 All other encodings are reserved. Negotiated Speed: This field indicates negotiated link speed. 1h = 2.5 Gb/s All other encodings are reserved. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 141: Slotcap-Slot Capabilities (D1:F0)

    Reserved R/WO Attention Button Present: This field indicates that an Attention Button is implemented on the chassis for this slot. The Attention Button allows the user to request hot-plug operations. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 142: Slotctl-Slot Control (D1:F0)

    1 = Enables the generation of hot plug interrupt or wake message on a presence detect changed event. Reserved Attention Button Pressed Enable: 0 = Disable. 1 = Enables the generation of hot plug interrupt or wake message on an attention button pressed event. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 143: Slotsts-Slot Status (D1:F0)

    1 = Presence Detect change is detected. This corresponds to an edge on the signal that corresponds to bit 6 of this register (Presence Detect State). Reserved R/WC Attention Button Pressed: 1 = Attention Button is pressed. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 144: Rctl-Root Control (D1:F0)

    0 = No SERR generated on receipt of correctable error. 1 = Indicates that an SERR should be generated if a correctable error is reported by any of the devices in the hierarchy associated with this Root Port, or by the Root Port itself. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 145: Rsts-Root Status (D1:F0)

    Requestor ID field asserted PME. Subsequent PMEs are kept pending until the status register is cleared by writing a 1 to this field. 15:0 PME Requestor ID: This field indicates the PCI requestor ID of the last PME 0000h requestor. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 146: Peglc-Pci Express*-G Legacy Control

    0 = Do not forward received GPE assert/deassert messages. 1 = Enable. Forward received GPE assert/deassert messages. These general GPE message can be received via the PCI Express* x16 Graphics Interface port from an external Intel device and will be subsequently forwarded to the ® Intel ICH6 (via Assert_GPE and Deassert_GPE messages on DMI).

  • Page 147: Vcech-Virtual Channel Enhanced Capability Header (D1:F0)

    The value of 0 in this field implies strict VC arbitration. Reserved R/WO Extended VC Count: This field indicates the number of (extended) Virtual 001b Channels in addition to the default VC supported by the device. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 148: Pvccap2-Port Vc Capability Register 2 (D1:F0)

    VC arbitration scheme is hardware fixed (in the root complex). This field can not be modified when more than one VC in the LPVC group is enabled. Reserved ® Intel 82925X/82925XE MCH Datasheet...

  • Page 149: Vc0Rcap-Vc0 Resource Capability (D1:F0)

    VC resource. In order to remove one or more TCs from the TC/VC Map of an enabled VC, software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link. TC0/VC0 Map: Traffic Class 0 is always routed to VC0. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 150: Vc0Rsts-Vc0 Resource Status (D1:F0)

    0 = Transactions with or without the No Snoop bit set within the TLP header are allowed on this VC. 1 = Any transaction without the No Snoop bit set within the TLP header will be rejected as an Unsupported Request. 14:0 Reserved ® Intel 82925X/82925XE MCH Datasheet...

  • Page 151: Vc1Rctl-Vc1 Resource Control (D1:F0)

    VC resource. In order to remove one or more TCs from the TC/VC Map of an enabled VC, software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link. TC0/VC1 Map: Traffic Class 0 is always routed to VC0. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 152: Vc1Rsts-Vc1 Resource Status (D1:F0)

    Extended Capability ID: Value of 0005h identifies this linked list item (capability 0005h structure) as being for PCI Express Link Declaration Capability. Note: See corresponding Egress Port Link Declaration Capability registers for diagram of Link Declaration Topology. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 153: Esd-Element Self Description (D1:F0)

    Element Self Description. This field reports 1 (to Egress port only as peer-to- peer capabilities in this topology are not reported). Reserved Element Type: This field indicates the type of the Root Complex Element. 0h = root port. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 154: Le1D-Link Entry 1 Description (D1:F0)

    RCRB). The link address specifies the 64-bit base address of the target RCRB. R/WO Link Valid: 0 = Link Entry is not valid and will be ignored. 1 = Link Entry specifies a valid link. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 155: Le1A-Link Entry 1 Address (D1:F0)

    Next Receive Sequence Number: This is the sequence number associated with 000h the TLP that is expected to be received next. 15:12 Reserved 11:0 Last Acknowledged Sequence Number: This is the sequence number FFFh associated with the last acknowledged TLP. § ® Intel 82925X/82925XE MCH Datasheet...
  • Page 156 Host-PCI Express* Graphics Bridge Registers (D1:F0) ® Intel 82925X/82925XE MCH Datasheet...

  • Page 157: System Address Map

    (4-KB window). • Device 1: Function 0: ⎯ MBASE1/MLIMIT1 – PCI Express port non-prefetchable memory access window. ⎯ PMBASE1/PMLIMIT1 – PCI Express port prefetchable memory access window. ⎯ IOBASE1/IOLIMIT1 – PCI Express port I/O access window. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 158: Legacy Address Range

    • 768 – 896 KB in 16-KB sections (total of 8 sections): Expansion Area • 896 – 960 KB in 16-KB sections (total of 4 sections): Extended System BIOS Area • 960-KB – 1-MB Memory: System BIOS Area ® Intel 82925X/82925XE MCH Datasheet...

  • Page 159: Dos Range (0H - 9_Ffffh)

    The MCH always positively decodes internally mapped devices, namely the PCI Express. Subsequent decoding of regions mapped to PCI Express or the DMI depends on the programming. This region is also the default for SMM space. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 160: Expansion Area (C_0000H-D_Ffffh)

    Table 9-1. Expansion Area Memory Segments Memory Segments Attributes Comments 0C0000h–0C3FFFh Add-on BIOS 0C4000h–0C7FFFh Add-on BIOS 0C8000h–0CBFFFh Add-on BIOS 0CC000h –0CFFFFh Add-on BIOS 0D0000h–0D3FFFh Add-on BIOS 0D4000h–0D7FFFh Add-on BIOS 0D8000h–0DBFFFh Add-on BIOS 0DC000h–0DFFFFh Add-on BIOS ® Intel 82925X/82925XE MCH Datasheet...

  • Page 161: Extended System Bios Area (E_0000H-E_Ffffh)

    PAM region. A snoop is generated on the FSB and the result is an IWB. Since the PAM region is “Read Disabled”, the default target for the memory read becomes DMI. The IWB associated with this cycle will cause the MCH to hang. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 162: Main Memory Address Range (1 Mb To Tolud)

    The range of physical main memory disabled by opening the hole is not remapped to the top of the memory; that physical main memory space is not accessible. This 15 MB–16 MB hole is an optionally enabled ISA hole. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 163: Tseg

    This address range, from the top of physical memory to 4 GB (top of addressable memory space supported by the MCH) is normally mapped via the DMI to PCI. Note: AGIP Aperture no longer exists with PCI Express. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 164: Apic Configuration Space (Fec0_0000H-Fecf_Ffffh)

    Since it is difficult to relocate an interrupt controller using plug-and-play software, fixed address decode regions have been allocated for them. Processor accesses to the default IOAPIC region (FEC0_0000h to FEC7_FFFFh) are always forwarded to DMI. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 165: Hseg (Feda_0000H-Fedb_Ffffh)

    PCI Express root complex hierarchy. This range will be aligned to a 256-MB boundary. BIOS must assign this address range such that it will not conflict with any other address ranges. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 166: Pci Express* Graphics Attach

    Unlike AGP4x, PCI Express has no concept of aperture for PCI Express devices. As a result, there is no need to translate addresses from PCI Express. Therefore, the MCH has no APBASE and APSIZE registers. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 167: System Management Mode (Smm)

    • TSEG Transaction Address SMM Space Enabled Transaction Address Space DRAM Space (DRAM) Compatible (C) 000A_0000h to 000B_FFFFh 000A_0000h to 000B_FFFFh High (H) FEDA_0000h to FEDB_FFFFh 000A_0000h to 000B_FFFFh TSEG (T) (TOLUD-STOLEN-TSEG) to (TOLUD-STOLEN-TSEG) to TOLUD-STOLEN TOLUD-STOLEN ® Intel 82925X/82925XE MCH Datasheet...

  • Page 168: Smm Space Restrictions

    Table 9-5. SMM Space Table Global Enable High Enable TSEG Enable Compatible High (H) TSEG (T) G_SMRAME H_SMRAM_EN TSEG_EN (C) Range Range Range Disable Disable Disable Enable Disable Disable Enable Disable Enable Disabled Enable Disable Disabled Enable Enable ® Intel 82925X/82925XE MCH Datasheet...

  • Page 169: Smm Control Combinations

    Processor write-back transactions (HREQ1# = 0) to enabled SMM address space must be written to the associated SMM DRAM, even though the space is not open and the transaction is not performed in SMM mode. This ensures SMM space cache coherency when cacheable extended SMM space is used. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 170: Smm Access Through Gtt Tlb

    I/O access is made to 4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh. HA16# is also asserted when an I/O access is made to 2 bytes from address 0FFFFh. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 171: Pci Express* I/O Address Mapping

    Express (Device 1), and/or to the DMI depending on BIOS programming. Priority for VGA mapping is constant in that the MCH always decodes internally mapped devices first. The MCH always positively decodes internally mapped devices, namely the PCI Express. § ® Intel 82925X/82925XE MCH Datasheet...
  • Page 172 System Address Map ® Intel 82925X/82925XE MCH Datasheet...

  • Page 173: Functional Description

    16 signals would normally be driven low on the bus, the corresponding HDINV# signal will be asserted and the data will be inverted prior to being driven on the bus. When the processor or ® Intel 82925X/82925XE MCH Datasheet...

  • Page 174: Apic Cluster Mode Support

    The system designer is free to populate or not to populate any rank on either channel, including either degenerate single channel case. Refer to Figure 10-1 for further clarification. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 175: Figure 10-1. System Memory Styles

    Channel A Channel B 0 MB 1280 MB 0 MB 2560 MB 256 MB 1280 MB 256 MB 2560 MB 512 MB 1024 MB 512 MB 2304 MB 512 MB 512 MB 512 MB 1792 MB ® Intel 82925X/82925XE MCH Datasheet...

  • Page 176: System Memory Configuration Register Overview

    • DRAM Control (CxDRCy): The x represents a channel, A (where x = 0) or B (where x = 1). A second register for a channel is differentiated by y, A or B. DRAM refresh mode, rate, and other controls are selected here. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 177: Dram Technologies And Organization

    • In Dual Channel Asymmetric mode, any DIMM slot may be populated in any order. • In Dual Channel Interleaved mode, any DIMM slot may be populated in any order, but the total memory in each channel must be the same. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 178: System Memory Supported Configurations

    Table 10-4 and Table 10-5 specify the host interface to memory interface address multiplex for the MCH. Refer to the details of the various DIMM configurations as described in Table 10-3. The address lines specified in the column header refer to the host (processor) address lines. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 179: Table 10-4. Dram Address Translation (Single Channel/Dual Asymmetric Mode)

    1 Gb x16 8 KB 512 MB 1 Gb x8 8 KB 1 GB NOTES: 1. b – ‘bank’ select bit 2. c – ‘column’ address bit 3. r – ‘row’ address bit ® Intel 82925X/82925XE MCH Datasheet...

  • Page 180: Table 10-5. Dram Address Translation (Dual Channel Symmetric Mode)

    4 KB 512 MB 1 Gb x8 8 KB 1 GB NOTES: 1. b – ‘bank’ select bit 2. c – ‘column’ address bit 3. h – channel select bit 4. r – ‘row’ address bit ® Intel 82925X/82925XE MCH Datasheet...

  • Page 181: Dram Clock Generation

    The algorithm and sequence of the adjustment cycles is handled by software. The MCH adjusts the DRAM driver impedance by issuing OCD commands to the DIMM and looking at the analog voltage on the DQ lines. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 182: Pci Express

    Transaction Layer and the Physical Layer. Responsibilities of Data Link Layer include link management, error detection, and error correction. 10.4.3 Physical Layer The Physical Layer includes all circuitry for interface operation, including driver and input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance matching circuitry. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 183: Power Management

    • PCI Express PLL – This PLL generates all PCI Express related clocks, including the Direct Media Interface that connects to the ICH6. This PLL uses the 100 MHz (GCLKIN) as a reference. Figure 10-2 illustrates the various clocks in the platform. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 184: Figure 10-2. System Clocking Example

    48 MHz USB USB PLL REF 14 MHz REF 14 MHz SIO LPC 25 MHz LCI Bit Clock 48/14 MHz ® Intel ICH6 High Def Audio REF 14 MHz Bit Clock AC97 PCI 33 MHz TPM LPC PCI 33 MHz...

  • Page 185: Electrical Characteristics

    2.5 V CMOS Supply Voltage with respect to V –0.3 2.65 NOTES: 1. Possible damage to the MCH may occur if the MCH temperature exceeds 150 °C. Intel does not guarantee functionality for parts that have exceeded temperatures above 150 °C due to specification violation. ®...

  • Page 186: Power Characteristics

    Compensation Voltage (1.8 V) Supply Current DDR2 System Memory Interface Resister — µA SUS_TTRC (DDR2) Compensation Voltage (1.8 V) Standby Supply Current System Memory PLL Analog (1.5 V) Supply — — — VCCA_SMPLL (DDR2) Current ® Intel 82925X/82925XE MCH Datasheet...

  • Page 187: Signal Groups

    HVREF, HSWING HRCOMP, HSCOMP Comp. Signals PCI Express* Interface Signal Groups PCI Express* Input PCI Express Interface: EXP_RXN(15:0), EXP_RXP(15:0), PCI Express Output PCI Express Interface: EXP_TXN(15:0), EXP_TXP(15:0) Analog EXP_COMP0 PCI Express I/F EXP_COMPI Compensation Signals ® Intel 82925X/82925XE MCH Datasheet...

  • Page 188: Figure 12-2. Intel

    1.5 V MCH Core Supply Voltage 2.5 V CMOS Supply VCC2 Voltage PLL Analog Supply VCCA_HPLL, VCCA_EXPPLL Voltages NOTES: 1. DDR2 533 with CAS timing of 3-3-3 operate at 1.9 V. 2. 82925X MCH signal only. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 189: General Dc Characteristics

    Host GTL+ Output High – 0.1 — OH_H Voltage (a, b) Host GTL+ Output Low — — OL_H 54 Ω Current (1–0.25)Rtt µA (a, c) Host GTL+ Input — — < LEAK_H Leakage Current Vpad < ® Intel 82925X/82925XE MCH Datasheet...
  • Page 190 Clocks, Reset, and Miscellaneous Signals Input Low Voltage — — Input High Voltage — — ±10 µA Input Leakage Current — — LEAK Input Capacitance — Input Low Voltage — — Input High Voltage 0.660 0.710 0.850 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 191 3. Specified at the measurement point and measured over any 250 consecutive Uls. The test load shown in Receiver compliance eye diagram of the PCI Express Interface Specification 1.0a should be used as the RX device when taking measurements. § ® Intel 82925X/82925XE MCH Datasheet...
  • Page 192 Electrical Characteristics ® Intel 82925X/82925XE MCH Datasheet...

  • Page 193: Ballout And Package Information

    MCH ballout sorted by ball number. Note: Balls that are listed as RSV are reserved. Board traces should be routed to these balls. Note: Balls that are listed as NC are No Connects. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 194: Figure 12-1. Intel ® 82925X/82925Xe Mch Ballout (Top View: Left Side)

    Ballout and Package Information ® Figure 12-1. Intel 82925X/82925XE MCH Ballout (Top View: Left Side) NC VSS RSV RSV VCC2 GCLKP EXP_TXN3 EXP_TXP3 EXP_TXN1 EXP_TXP1 VCCA_DPLLA VCCA_HPLL VCCA_EXPPLL NC VSS VSS VSS VSS VSS VSS VSS VSS RSV VSS GCLKN...

  • Page 195: Figure 12-2. Intel ® 82925X/82925Xe Mch Ballout (Top View: Right Side)

    Ballout and Package Information ® Figure 12-2. Intel 82925X/82925XE MCH Ballout (Top View: Right Side) VTT VTT VTT VTT VSS NC HD48 HD61 HD57 HD55 HD53 HVREF HSWING VTT VTT VTT VTT HD63 HD54 HD51 HD52 HD15 HD13 HD11 HRCOMP...

  • Page 196: Table 12-1. Mch Ballout Sorted By Signal Name

    EXP_TXN15 HA12# EXP_RXN11 EXP_TXN2 HA13# EXP_RXN12 EXP_TXN3 HA14# EXP_RXN13 EXP_TXN4 HA15# EXP_RXN14 EXP_TXN5 HA16# EXP_RXN15 EXP_TXN6 HA17# EXP_RXN2 EXP_TXN7 HA18# EXP_RXN3 EXP_TXN8 HA19# EXP_RXN4 EXP_TXN9 HA20# EXP_RXN5 EXP_TXP0 HA21# EXP_RXN6 EXP_TXP1 HA22# EXP_RXN7 EXP_TXP10 HA23# ® Intel 82925X/82925XE MCH Datasheet...
  • Page 197 HD47 HREQ0# HD10 HD48 HREQ1# HD11 HD49 HREQ2# HD12 HD50 HREQ3# HD13 HD51 HREQ4# HD14 HD52 HRS0# HD15 HD53 HRS1# HD16 HD54 HRS2# HD17 HD55 HSCOMP HD18 HD56 HSWING HD19 HD57 HTRDY# HD20 HD58 HVREF ® Intel 82925X/82925XE MCH Datasheet...
  • Page 198 AM12 AM15 AB33 AM18 AD32 AM21 PWROK AM24 RSTIN# RSV_TP0 AE16 RSV_TP1 AH15 AP35 RSV_TP2 AL15 RSV_TP3 AK15 SBS_A0 AN27 AR34 SBS_A1 AR27 AR35 SBS_A2 AR20 SBS_B0 AR16 SBS_B1 AN16 SBS_B2 SCAS_A# AP29 SCAS_B# AP18 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 199 SDQ_A19 RSV (82925XE) SCS_B2# AN33 SDQ_A20 SCKE_A0 AP19 SCS_B3# AP34 SDQ_A21 SCKE_A1 AN19 SDM_A0 SDQ_A22 SCKE_A2 AN18 SDM_A1 SDQ_A23 SCKE_A3 AR19 SDM_A2 SDQ_A24 AE17 SCKE_B0 SDM_A3 AF17 SDQ_A25 AF16 SCKE_B1 SDM_A4 AJ33 SDQ_A26 AL17 SCKE_B2 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 200 SDQ_B32 AF24 SDQS_A3 AH16 SDQ_A59 SDQ_B33 AG24 SDQS_A3# AG17 SDQ_A60 SDQ_B34 AL26 SDQS_A4 AK27 SDQ_A61 SDQ_B35 AJ26 SDQS_A4# AJ28 SDQ_A62 SDQ_B36 AF23 SDQS_A5 AG35 SDQ_A63 SDQ_B37 AD23 SDQS_A5# AG33 SDQ_B00 AG11 SDQ_B38 AL25 SDQS_A6 AA34 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 201 RSV (82925XE) SODT_B0 AN34 SMA_A0 AN26 SODT_B1 AL34 SMA_A1 AP25 SODT_B2 AL35 SMA_A2 AN25 SODT_B3 AL33 SMA_A3 AR24 SRAS_A# AP27 SMA_A4 AP23 SRAS_B# AN17 SMA_A5 AN22 SRCOMP0 SMA_A6 AR23 SRCOMP1 SMA_A7 AN21 SVREF0 SMA_A8 AN23 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 202 VCC_EXP AB17 VCC_EXP AB18 VCC_EXP AB19 VCC_EXP VCC_EXP AB20 VCC2 AB21 VCCA_DPLLA AB22 VCCA_DPLLB AB23 VCCA_EXPPLL AB24 VCCA_HPLL VCCA_SMPLL VCCSM AK35 VCCSM AL12 VCCSM AM10 VCCSM AM11 VCCSM AM13 VCCSM AM14 VCCSM AM16 VCCSM AM17 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 203 VCCSM AP28 AD34 VCCSM AE12 VCCSM AR10 AE21 VCCSM AR14 AE22 VCCSM AR18 AE23 VCCSM AR22 AE24 VCCSM AR26 AE28 VCCSM AR31 AE32 VCCSM AR33 VCCSM VCCSM AM25 AA26 AA27 AB25 AB28 AB30 AB32 AB35 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 204 Signal Name Ball # AJ16 AJ19 AJ22 AF10 AJ27 AF18 AF21 AF26 AF29 AF31 AF32 AF35 AG12 AG13 AG15 AG16 AG18 AG19 AG21 AG22 AH11 AH14 AH18 AH20 AH22 AH26 AH29 AH32 AH33 AJ10 AJ13 AJ15 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 205 Ball # Signal Name Ball # AL10 AL13 AL16 AL19 AL24 AL32 AM28 AM31 AR13 AR17 AR21 AA10 AR25 AA11 AA15 AR30 AA17 AA19 AA25 AJ30 AJ32 AJ35 AK11 AK14 AK17 AK20 AK23 AK25 AK26 AK30 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 206 Table 12-1. MCH Ballout Table 12-1. MCH Ballout Table 12-1. MCH Ballout Sorted By Signal Name Sorted By Signal Name Sorted By Signal Name Signal Name Ball # Signal Name Ball # Signal Name Ball # ® Intel 82925X/82925XE MCH Datasheet...

  • Page 207: Table 12-2. Mch Ballout Sorted By Ball Number

    EXP_TXN4 EXP_TXP4 GCLKP EXP_TXN2 VCCA_DPLLA EXP_TXP2 VCC2 GCLKN EXP_TXN0 VCCA_EXPPLL EXP_TXP0 VCCA_DPLLB — VCCA_HPLL VCCA_SMPLL MTYPE HSWING HVREF HD48 HRCOMP HD61 HD63 HD57 HDINV3# — HD55 HD54 HD58 HD59 HD53 HDSTBP3# HD49 — HD51 HD56 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 208 HD25 HD17 HD50 HD18 HD24 HD14 HD16 HD12 HBPRI# HD10 HPCREQ# — HREQ1# EXP_TXN5 — HDSTBP0# HDINV0# HDSTBN0# EXP_RXP5 EXP_TXP6 EXP_TXP7 EXP_RXN5 EXP_TXN6 EXP_RXN3 EXP_RXN2 EXP_RXP3 EXP_RXP0 EXP_RXP2 EXP_RXN0 BSEL2 BSEL1 HD47 HDSTBN2# HSCOMP HD62 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 209 HD41 HD40 HDSTBN1# HCPURST# HD23 HD26 HD37 HD22 HDSTBP1# HREQ4# HD20 HA6# HD19 HREQ0# HREQ3# HA3# HA7# HREQ2# EXP_TXN7 EXP_TXP8 EXP_TXP9 EXP_RXN6 EXP_TXN8 EXP_TXN9 EXP_RXP6 EXP_TXP10 EXP_RXN7 EXP_RXN8 EXP_RXP7 EXP_RXP8 EXP_RXN1 EXP_RXP1 HD45 BSEL0 HD46 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 210 HD31 HDINV1# HD21 HD28 HD30 HA13# HA5# HA14# HD29 HA18# HADSTB0# HA4# HRS2# HA8# HA12# HA9# HDEFER# HA15# HA11# EXP_TXP11 HRS0# HLOCK# EXP_TXN10 EXP_TXN11 HHIT# HDBSY# EXP_TXP12 EXP_TXP13 EXP_RXN9 EXP_RXN10 EXP_TXN12 EXP_RXP9 EXP_RXP10 EXP_RXN12 EXP_RXP12 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 211 EXP_RXN14 DREFCLKP ICH_SYNC# EXP_RXP11 HD42 HD38 HD36 HCLKN HCLKP HA20# HA16# HA19# HADSTB1# HA10# HA22# HADS# HA23# HDRDY# HA24# — HA21# HBNR# HA26# EXP_TXN13 HTRDY# HHITM# HEDRDY# EXP_TXP14 EXP_TXP15 HRS1# EXP_RXN13 EXP_TXN14 EXP_TXN15 EXP_RXP13 DMI_TXP0 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 212 EXP_RXP15 SDQ_A63 DMI_TXN0 DMI_TXN1 DMI_TXP2 EXP_RXN11 DMI_RXP0 DMI_RXN1 DMI_RXN0 DMI_RXP1 DMI_RXN3 HA25# HA17# SCB_A4 (82925X) HA30# RSV (82925XE) HA27# SCB_A5 (82925X) SDQ_B63 RSV (82925XE) HA31# SDQ_A58 HA29# HBREQ0# HA28# SDQ_A59 SDQS_A8# (82925X) RSV (82925XE) SDQ_A62 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 213 SDQ_B57 RSV (82925XE) SDQ_A57 DMI_TXN2 SDM_B7 SDQ_A56 DMI_TXP3 SDQ_A61 VCC_EXP SDQ_A51 VCC_EXP DMI_RXP2 SDQ_A60 VCC_EXP DMI_RXN2 VCC_EXP VCC_EXP VCC_EXP DMI_TXN3 DMI_RXP3 VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP EXP_COMPI VCC_EXP VCC_EXP EXP_COMPO SDQ_B58 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 214 AB29 AA32 SDQ_A54 RSV (82925XE) AA33 SDM_A6 AB30 AA34 SDQS_A6 AB31 SDQS_B6 AA35 SDQS_A6# AB32 AB33 AB34 SCLK_A5# AB35 AA10 AA11 AA12 AA13 AB10 AA14 AB11 AA15 AB12 AA16 AB13 AA17 AC10 AB14 AA18 AC11 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 215 AE28 AC33 SCLK_A5 AD31 SDQ_A48 AE29 SDQ_B53 AC34 SCLK_A2 AD32 AE30 AC35 SCLK_A2# AD33 — AE31 SDQ_B52 AD34 AE32 AD35 SDQ_A49 AE33 SDQ_A43 SDQ_A5 AE34 SDQ_A53 SDQ_A4 AE35 SDQ_A52 SDQ_A0 SDM_A0 SOCOMP1 SDQ_A1 SVREF0 SOCOMP0 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 216 AG29 AH27 SDQ_A34 AF32 AG30 SDQ_B46 AH28 SDQS_B5 AF33 SDQ_A42 AG31 SDQ_B42 AH29 AF34 SDQ_A47 AG32 SDQ_A46 AH30 SDQS_B5# AF35 AG33 SDQS_A5# AH31 SDM_B5 SDQS_A0 AG34 SDM_A5 AH32 SDQS_A0# AG35 SDQS_A5 AH33 SDQ_A6 AH34 SDQ_A40 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 217 AL16 RSV (82925XE) AK20 AL17 SDQ_A26 SCB_B3 (82925X) AJ24 SDQS_B8 (82925X) AK21 AL18 SDQ_B26 RSV (82925XE) RSV (82925XE) AL19 AJ25 SDQ_B39 AK22 SCLK_B3# SCB_B4 (82925X) AL20 AJ26 SDQ_B35 AK23 RSV (82925XE) AJ27 AK24 AJ28 SDQS_A4# ® Intel 82925X/82925XE MCH Datasheet...
  • Page 218 SDQ_A16 AM10 VCCSM SCKE_B3 SDM_A2 AM11 VCCSM SBS_B2 SDQS_A2 AM12 AN10 SMA_B12 VCCSM AM13 VCCSM AN11 SMA_B5 SCKE_B1 AM14 VCCSM AN12 — AP10 SMA_B11 AM15 AN13 SMA_B4 AP11 SMA_B9 AM16 VCCSM AN14 SMA_B2 AP12 VCCSM ® Intel 82925X/82925XE MCH Datasheet...

  • Page 219: Package Information

    The MCH package measures 37.5 mm × 37.5 mm. The 1210 balls are located in a non-grid pattern. For example, the ball pitch varies from 31.8 mils to 43.0 mils, depending on the X-axis or Y-axis direction. Figure 12-3 shows the physical dimensions of the package. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 220: Figure 12-3. Mch Package Dimensions

    Ballout and Package Information Figure 12-3. MCH Package Dimensions ® Intel 82925X/82925XE MCH Datasheet...

  • Page 221: Testability

    SM XOR 3 SDQS_B5# SM XOR 5 SDQS_B6 SM XOR 3 SDQS_B6# SM XOR 5 SDQS_B7 SM XOR 3 SDQS_B7# SM XOR 5 SDQS_B8 (82925X) SM XOR 7 SDQS_B8# (82925X) SM XOR 5 RSV (82925XE) RSV (82925XE) ® Intel 82925X/82925XE MCH Datasheet...

  • Page 222: Xor Test Mode Initialization

    The following tables show the XOR chains. The last section in this chapter has a pin exclusion list. The chain files are golden, if there is a pin missing from the chain files and exclusion list, it should be added to the exclusion list. ® Intel 82925X/82925XE MCH Datasheet...

  • Page 223: Table 13-3. Xor Chain #0

    Signal Name ICH_SYNC# EXTTS# HCPURST# HD44 HD42 HD43 HD47 HD38 HD39 HDINV2# HD46 HDSTBP2# HDSTBN2# HD45 HD34 HD36 HD35 HD40 HD41 HD33 HD32 HD37 HD48 HD55 HD60 HDINV3# HDSTBP3# HDSTBN3# HD58 HD51 HD24 HD17 HD25 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 224 Signal Name HD19 HD23 HD22 HDSTBP1# HDSTBN1# HD21 HD27 HD28 HD31 HD30 HDINV1# HD26 HD29 HD15 HA6# HA3# HA13# HA5# HA15# HREQ4# HA4# HA11# HA14# HA10# HREQ0# HBPRI# HDEFER# HEDRDY# XOR Chain #0 Output BSEL2 ® Intel 82925X/82925XE MCH Datasheet...

  • Page 225: Table 13-4. Xor Chain #1

    Chain Pin Count Ball Number Signal Name HD57 HD61 HD54 HD63 HD62 HD59 HD49 HD56 HD53 HD50 HD52 HD18 HD16 HD20 HD11 HD13 HD14 HD12 HD10 HDINV0# HDSTBP0# HDSTBN0# HA7# HREQ2# HA8# HADSTB0# HREQ3# HPCREQ# ® Intel 82925X/82925XE MCH Datasheet...
  • Page 226 HRS2# HRS0# HLOCK# HDRDY# HADS# HHIT# HBNR# HDBSY# HHITM# HRS1# HTRDY# HBREQ0# HA21# HA26# HA28# HREQ1# HA27# HA20# HA19# HA24# HA29# HADSTB1# HA18# HA16# HA31# HA25# HA23# HA30# HA22# HA17# XOR Chain #1 Output RSV_M16 ® Intel 82925X/82925XE MCH Datasheet...

  • Page 227: Table 13-5. Xor Chain #2

    RSV (82925XE) SCB_A1 (82925X) RSV (82925XE) SCB_A0 (82925X) RSV (82925XE) SCB_A5 (82925X) RSV (82925XE) SCB_A4 (82925X) RSV (82925XE) AA34 SDQS_A6 SDQ_A51 SDQ_A55 SDQ_A50 AD35 SDQ_A49 AE35 SDQ_A52 AE34 SDQ_A53 AA33 SDM_A6 AA32 SDQ_A54 AD31 SDQ_A48 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 228 AH35 SDQ_A41 AJ34 SDQ_A45 AG34 SDM_A5 AE33 SDQ_A43 AF33 SDQ_A42 AG32 SDQ_A46 AH34 SDQ_A40 AK34 SDQ_A44 AG35 SDQS_A5 AR29 SCS_A0# AN32 SODT_A3 AN29 SODT_A2 AP32 SODT_A1 AP30 SODT_A0 AJ28 SDQS_A4# XOR Chain #2 Output RSV_F15 ® Intel 82925X/82925XE MCH Datasheet...

  • Page 229: Table 13-6. Xor Chain #3

    SDQ_B53 AF27 SDQ_B48 AB26 SDQ_B51 AC28 SDQ_B54 AD24 SDM_B6 AN33 SCS_B2# AD29 SCLK_B5# AE25 SCLK_B2# AE26 SCLK_B2 AP34 SCS_B3# AP33 SCS_B0# AM33 SCS_B1# AL33 SODT_B3 AL34 SODT_B1 AL35 SODT_B2 AN34 SODT_B0 AF30 SDQ_B43 AK32 SDQ_B40 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 230 Signal Name AH31 SDM_B5 AK33 SDQ_B45 AJ31 SDQ_B41 AG28 SDQ_B47 AJ29 SDQ_B44 AG31 SDQ_B42 AH28 SDQS_B5 AM34 SMA_B13 AJ25 SDQ_B39 AL25 SDQ_B38 AJ26 SDQ_B35 AL26 SDQ_B34 AF23 SDQ_B36 AG24 SDQ_B33 XOR Chain #3 Output MTYPE ® Intel 82925X/82925XE MCH Datasheet...

  • Page 231: Table 13-7. Xor Chain #4

    SDQ_A37 AK29 SDQ_A32 AP29 SCAS_A# AN28 SWE_A# AR28 SCS_A2# AR27 SBS_A1 AP27 SRAS_A# AN27 SBS_A0 AM30 SCLK_A0# AL29 SCLK_A0 AL28 SCLK_A3 AK28 SCLK_A3# AN25 SMA_A2 AP26 SMA_A10 AN26 SMA_A0 AN30 SMA_A13 AP25 SMA_A1 AP23 SMA_A4 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 232 Pin Count Ball Number Signal Name AR24 SMA_A3 AR23 SMA_A6 AN23 SMA_A8 AH16 SDQS_A3 AH17 SDQ_A27 AL17 SDQ_A26 AF16 SDQ_A25 AE17 SDQ_A24 AD17 SDQ_A29 AN18 SCKE_A2 SDQS_A2# SCLK_A1# SDQS_A1# SDQS_A0# XOR Chain #4 Output RSV_A16 ® Intel 82925X/82925XE MCH Datasheet...

  • Page 233: Table 13-8. Xor Chain #5

    SCB_B6 (82925X) AL21 RSV (82925XE) SCB_B5 (82925X) AK18 RSV (82925XE) SCB_B2 (82925X) AJ23 RSV (82925XE) SCB_A7 (82925X) AB29 RSV (82925XE) SCB_B3 (82925X) AJ24 RSV (82925XE) SCB_B4 (82925X) AL20 RSV (82925XE) SCB_B0 (82925X) AJ20 RSV (82925XE) ® Intel 82925X/82925XE MCH Datasheet...
  • Page 234 RSV (82925XE) AN17 SRAS_B# AP18 SCAS_B# AP17 SWE_B# AR16 SBS_B0 AN16 SBS_B1 AN14 SMA_B2 AN15 SMA_B0 AP15 SMA_B10 AR15 SMA_B1 AP14 SMA_B3 AN13 SMA_B4 SCKE_B0 AG14 SDQS_B2# SCLK_B1# SDQS_B1# SDQS_B0# XOR Chain #5 Output RSV_B15 ® Intel 82925X/82925XE MCH Datasheet...

  • Page 235: Table 13-9. Xor Chain #6

    AP21 SMA_A11 AP22 SMA_A9 AN22 SMA_A5 AR20 SBS_A2 AN21 SMA_A7 AN20 SMA_A12 AP19 SCKE_A0 AR19 SCKE_A3 SDQS_A2 SDQ_A18 SDQ_A19 SDQ_A23 SDQ_A22 SDM_A2 SDQ_A17 SDQ_A16 SDQ_A21 SDQ_A20 SCLK_A4# SCLK_A4 SCLK_A1 SDQ_A11 SDQ_A15 SDQ_A14 SDQ_A10 SDQ_A9 SDQ_A8 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 236 Testability Chain Pin Count Ball Number Signal Name SDQ_A13 SDQ_A12 SDM_A1 SDQS_A1 SDQS_A0 SDQ_A6 SDM_A0 SDQ_A7 SDQ_A2 SDQ_A3 SDQ_A1 SDQ_A0 SDQ_A4 SDQ_A5 XOR Chain #6 Output RSV_C14 ® Intel 82925X/82925XE MCH Datasheet...

  • Page 237: Table 13-10. Xor Chain #7

    SMA_B5 SCKE_B2 SCKE_B1 SCKE_B3 AE14 SDQ_B19 AF14 SDQ_B18 AK13 SDQ_B22 AH12 SDM_B2 AD14 SDQ_B17 AL14 SDQ_B23 AD12 SDQ_B20 AF13 SDQ_B16 AE13 SDQ_B21 AH13 SDQS_B2 AL11 SCLK_B4# AJ11 SCLK_B4 SCLK_B1 SDQ_B9 SDQ_B13 SDQ_B12 AK10 SDQ_B8 SDQ_B10 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 238 Testability Chain Pin Count Ball Number Signal Name SDQ_B15 SDQ_B14 SDM_B1 AF12 SDQ_B11 SDQS_B1 SDQS_B0 AE11 SDQ_B4 AF11 SDQ_B5 AG10 SDQ_B1 SDQ_B2 SDQ_B3 SDQ_B6 AH10 SDM_B0 AG11 SDQ_B0 SDQ_B7 XOR Chain #7 Output RSV_K15 ® Intel 82925X/82925XE MCH Datasheet...

  • Page 239: Table 13-11. Xor Chain #8

    Signal Name EXP_RXN0 EXP_TXN0 EXP_RXN1 EXP_TXN1 EXP_RXN2 EXP_TXN2 EXP_RXN3 EXP_TXN3 EXP_RXN4 EXP_TXN4 EXP_RXN5 EXP_TXN5 EXP_RXN6 EXP_TXN6 EXP_RXN7 EXP_TXN7 EXP_RXN8 EXP_TXN8 EXP_RXN9 EXP_TXN9 EXP_RXN10 EXP_TXN10 EXP_RXN11 EXP_TXN11 EXP_RXN12 EXP_TXN12 EXP_RXN13 EXP_TXN13 EXP_RXN14 EXP_TXN14 EXP_RXN15 EXP_TXN15 EXP_RXP0 ® Intel 82925X/82925XE MCH Datasheet...
  • Page 240 EXP_RXP1 EXP_TXP1 EXP_RXP2 EXP_TXP2 EXP_RXP3 EXP_TXP3 EXP_RXP4 EXP_TXP4 EXP_RXP5 EXP_TXP5 EXP_RXP6 EXP_TXP6 EXP_RXP7 EXP_TXP7 EXP_RXP8 EXP_TXP8 EXP_RXP9 EXP_TXP9 EXP_RXP10 EXP_TXP10 EXP_RXP11 EXP_TXP11 EXP_RXP12 EXP_TXP12 EXP_RXP13 EXP_TXP13 EXP_RXP14 EXP_TXP14 EXP_RXP15 EXP_TXP15 XOR Chain #8 Output BSEL1 ® Intel 82925X/82925XE MCH Datasheet...

  • Page 241: Table 13-12. Xor Chain #9

    Testability Table 13-12. XOR Chain #9 Chain Pin Count Ball Number Signal Name DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0 DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1 DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2 DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3 XOR Chain #9 Output BSEL0 ® Intel 82925X/82925XE MCH Datasheet...

  • Page 242: Pads Excluded From Xor Mode(S)

    Table 13-13. XOR Pad Exclusion List Miscellaneous 3GIO GCLKN HCLKN SRCOMP1 DREFCLKN GCLKP HCLKP SRCOMP0 DREFCLKP EXP_COMPO HRCOMP SMVREF1 BLUE EXP_COMPI HSCOMP SMVREF0 BLUE# HVREF SOCOMP1 GREEN HSWING SOCOMP0 GREEN# SM_SLEWOUT1 SM_SLEWOUT0 RED# SM_SLEWIN1 RSTIN# SM_SLEWIN0 HSYNC VSYNC REFSET ® Intel 82925X/82925XE MCH Datasheet...

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