Cycle Control - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
CPU-CACHE CHIP SET
ClK, SNPClK,
OR STROBED
TO/FROM
SNOOP BUS
ADDRESS
ADDRESS CONTROL
,- ................. -,
: BUFFERS :
• (OPTIONAL) •
·
.
·
................... . .
TO/FROM
ADDRESS BUS
(ClK)
CONTROL
ClK
CYCLE
CONTROL
MEMORY
BUS
CYCLE
CONTROL
TO/FROM
CONTROL BUS
(MClK OR STROBED)
DATA
CONTROL DATA
,-
..................
,
: BUFFERS :
• (OPTIONAL) •
· .
·
................... ..
TO/FROM
DATA BUS
Figure 5-1. MBC Block Diagram
5.1.1.
Cycle Control
CUB3l
The 82496 Cache Controller/82491 Cache SRAM can handle unlocked read and write hits to
the [E] and [M] states and unlocked read hits to [S] state independently of the MBC and the
system. All other cycles require access to memory bus, arbitrated by the MBC.
Cycles on the memory bus are requested by the 82496 Cache Controller to the MBC with
address and data strobe outputs. The memory bus controller responds to the request with cycle
progress signals and cycle attributes (sampled by the 82496 Cache Controller with select
progress signals). Figure 5-2 shows the signals used by the 82496 Cache Controller to request
memory bus cycles, and the signals expected from the MBC in order for a cycle to complete
normally.
5-2
I