Intel 82496 CACHE CONTROLLER User Manual page 208

HARDWARE INTERFACE
Relation to Other Signals
Pin Symbol Relation to Other Signals
BGT# CRDY# follows BGT#.
CRDY# follows BGT# by three ClKs for line fill or allocation cycles.
BRDY# CRDY# for a cycle N+ 1 must be sampled active after the last BRDY# for cycle N.
CRDY# for cycle N can be before, with, or after the BRDY#(s) for that cycle.
CADS# CRDY# is required for all memory bus cycles initiated by CADS#.
CDTS# CRDY# follows CDTS#.
CNA# CNA# is recognized between BGT#/CDTS# (the later of the two) and CRDY#.
KWEND# CRDY# follows KWEND# for line fill or write-through cycles with potential
allocation (PAllC#= 0).
MBRDY#
For read cycles, MBRDY# fills the memory buffer in use. CRDY# empties the
current memory cycle buffer (read or write cycles) and makes it available for new
cycles.
MEOC# MEOC# for cycle N must be sampled with or before CRDY# for that cycle.
MEOC# for cycle N+ 1 must be sampled at least one ClK after CRDY# for cycle N.
CRDY# may be asserted with MEOC#, which may be asserted with the last
MBRDY#.
SlFTST#
CRDY# shares a pin with the 82496 Cache Controller SlFTST# input.
SNPADS#
CRDY# is required for all memory bus cycles initiated by SNPADS#.
SWEND# CRDY# activation represents only the end of the current cycle on the memory bus,
and does not imply the closure of the snooping window (SWEND#).
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