Intel 82496 CACHE CONTROLLER User Manual page 331

HARDWARE INTERFACE
5.2.2.136. TCK
TCK Test ClK
JTAG boundary scan test Clock.
Input to Pentium processor (pin T04), 82496 Cache Controller (pin 004), and
82491 Cache SRAM (pin 3)
Pentium processor, 82496 Cache Controller, 82491 Cache SRAM internal Pull-ups
Signal Description
TCK provides the clocking function required by the JT AG boundary scan feature. TCK is used
to clock state information and data into and out of the Pentium processor, 82496 Cache
Controller and 82491 Cache SRAM components. State select inforniation and data are clocked
into the component on the rising edge of TCK on TMS and TDI, respectively. Data is clocked
out of the Pentium processor CPU-Cache Chip Set on the falling edge of TCK on TDO.
In addition to using TCK as a free running clock, it may be held in a LOW state indefinitely as
described in IEEE 1149.1. While TCK is held in the LOW state, the boundary scan latches
retain their state.
When boundary scan is not used, TCK should be tied low.
When Sampled
TCK is a clock signal and is used as a reference for sampling other boundary scan signals.
Relation to Other Signals
Pin Symbol Relation to Other Signals
TOI TMS and TOI are sampled on the rising edge of TCK.
TOO TOO is driven on the falling edge of TCK.
TMS TMS and TOI are sampled on the rising edge of TCK.
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