Cdata[7:0] - Intel 82496 CACHE CONTROLLER User Manual

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HARDWARE INTERFACE
5.2.2.30. CDATA[7:0]
CDATA[7:0] Cache Data Pins
I/O data bus between the 82491 Cache SRAM and the Pentium processor.
Input/Output between Pentium processor D[63:0] and 82491 Cache SRAM (pins
57,52,51,46,55,49,54,48)
Synchronous to ClK
Signal Description
The 82491 Cache SRAM CDATA[7:0) signals connect to the Pentium processor data pins
D[63:0). The specific data pin connections are cache size and configuration dependent.
For cache configurations which only require 4 MDAT A pins, bits 3-0 are used. Unused
CDATA[7:4) pins must be tied to either VSS or VCC through resistors.
Refer to the Pentium™ Processor Data Book for a detailed description of the Pentium
processor D[63:0) signals.
When Driven/Sampled
CDATA[7:0) are sampled with proper valid delays in the CLK that BRDYC# is driven to the
Pentium processor. CDATA[7:0) are driven by the 82491 Cache SRAM with proper setup and
hold times in the CLK that BRDYC# is driven to the processor. Refer to the Pentium
rM
Processor Data Book for data signal driving/sampling requirements.
Relation to Other Signals
Pin Symbol
Relation to Other Signals
BE[7:0]# The Pentium processor Byte Enable outputs are connected to the 82491 Cache
SRAM CDATA[7:4] pins for 82491 Cache SRAMs configured to be data parity
devices. Refer to section 5.1.6.5.
DP[7:0] The Pentium processor Data parity signals are connected to the 82491 Cache
SRAM CDATA[3:0] pins for 82491 Cache SRAMs configured to be data parity
devices. Refer to section 5.1.6.5.
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