Mesi Cache Consistency Protocol Model - Intel 82496 CACHE CONTROLLER User Manual

COMPONENT OPERATION
performance uniprocessor or multiprocessor systems. The 82496 Cache Controller/82491
Cache SRAM secondary cache provides 8 or 16 82491 Cache SRAM components and a 82496
Cache Controller cache controller that offers full multiprocessor cache consistency support.
Because the 82496 Cache Controller implements a write-back cache architecture, the 82496
Cache Controller/82491 Cache SRAM will at times contain data that has not yet been written
back into main memory. The 82496 Cache Controller is designed to ensure that all of the bus
masters in a shared memory system are prevented from reading invalid data.
Multiprocessor systems must not only provide cache consistency, but minimize memory bus
access as well. Otherwise, bus masters combine to create a resource bottleneck that can
degrade the performance potential of mUltiple execution units.
The cache consistency protocol used by the 82496 Cache Controller is designed both to ensure
cache consistency and to keep memory bus utilization to a minimum. The protocol is based on
several common protocols.
The 82496 Cache Controller protocol is implemented by assigning state bits for each cached
line. These states are affected both by CPU initiated operations and by snoop operations per-
formed in response to requests from other bus masters.
3.4. MESI CACHE CONSISTENCY PROTOCOL MODEL
The description that follows applies to memory read and write cycles only. I/O and special
cycles bypass the cache altogether.
The 82496 Cache Controller/82491 Cache SRAM follows the MESI protocol which is used to
indicate whether a given cache line has been modified [M], not modified but valid (exclusive
[E] or shared [S]), or is invalid [I].
The MESI states are explained in more detail as follows:
[M] - MODIFIED
[E] . EXCLUSIVE
[S]· SHARED
3-2
The [M] state indicates that a line is exclusive to the 82496 Cache
Controller/82491 Cache SRAM cache and has been modified.
Therefore, the corresponding line in main memory is invalid. This
cache line can be modified further without memory bus access,
thereby reducing bus traffic. Because the data is exclusive to the
82496 Cache Controller/82491 Cache SRAM's cache, the 82496
Cache Controller/82491 Cache SRAM must at some point write this
information back to main memory.
The [E] state indicates that a particular line is available in the 82496
Cache Controller/82491 Cache SRAM cache exclusively and that the
line has not been modified. Therefore, the corresponding main
memory line is valid. A write changes this line to the [M] state
without accessing the memory bus.
The [S] state indicates that a particular line may also exist in other
system caches. A shared line may be read from the cache without
requiring main memory access. Writing to a shared line updates the
cache, but also requires that the 82496 Cache Controller/82491 Cache
SRAM generate a write-through to update main memory and invali-
date the line where it exists in other caches.
I