Tag State And Cycles.resulting From State Transitions; Tag State; Cycles Resulting From State Transitions - Intel 82496 CACHE CONTROLLER User Manual

COMPONENT OPERATION
3.7.3. Tag State and Cycles Resulting from State Transitions
3.7.3.1. TAG STATE
The following is a 82496 Cache Controller tag state change that may occur with 82496 Cache
Controller/82491 Cache SRAM state transitions. Note that other tag state changes are not
documented here, as they are not used in the tables that follow.
• TRO
(Tag Read Only, 82496 Cache Controller Tag bit): When set indicates that the 1 or 2
(if 2 lines per sector) lines associated with the current tag are Read-Only lines.
3.7.3.2. CYCLES RESULTING FROM STATE TRANSITIONS
As a function of State Changes, the 82496 Cache Controller may execute the following cycles:
• BINV: CPU Back Invalidation Cycle (Snoop to Pentium processor with INV active)
• INQR:
Pentium processor Inquire Cycle to search for a CPU modified line.
•
•
•
•
3-12
NOTE
An inquire cycle may be executed with INV active, performing a back-
invalidation simultaneously.
WBCK:
82496 Cache Controller Write-Back Cycle. The 82496 Cache Controller generates
a writeback cycle when MODIFIED data cached in the 82496 Cache Controller needs to
be copied back into main memory. A write-back cycle affects a complete 82496 Cache
Controller line.
WTHR:
82496 Cache Controller Write Through Cycle. This is a memory bus write cycle
in response to a processor write. It mayor may not affect the cache SRAM (update). In a
write-through cycle, the 82496 Cache Controller drives the Memory Bus with the same
Address, Data and Control signals as the CPU does on the CPU Bus. Main memory will be
updated, and other caches will invalidate their copies.
RTHR:
82496 Cache Controller Read Through cycle. This is a special read cycle to
support locked reads to lines that hit the 82496 Cache Controller cache. The 82496 Cache
Controller will request a Memory Bus cycle for lock synchronization reasons. Data will
be supplied from the memory BUS except if the current line is in the [M] state. If so, data
will be supplied to the Pentium processor from the 82496 Cache Controller/82491 Cache
SRAM.
LFIL: 82496 Cache Controller Cache line fill. The 82496 Cache Controller will generate
Memory Bus cycles to fetch a new line and deposit it into the cache.
I