Klock - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.69. KLOCK#
KlOCK# 82496 Cache Controller lOCK#
Request for lOCKed cycle.
Output from 82496 Cache Controller (pin 004)
Synchronous to ClK
Glitch Free
Signal Description
KLOCK# indicates an 82496 Cache Controller request for the MBC to execute a locked cycle.
KLOCK# follows the CPU LOCK# request.
KLOCK# is simply a one-CLK flow-through version of the CPU LOCK# signal if the Memory
Bus is free. The 82496 Cache Controller activates KLOCK# with CADS# of the first cycle of a
LOCKed operation and remains active through CADS# of the last cycle of the LOCKed
operation (i.e. the write of a processor read-modify-write sequence) (see Figure 5-26).
Unlike the Intel486 DX CPU, the Pentium processor automatically inserts at least one idle
clock between two consecutive locked operations to allow the LOCK# and KLOCK# signals to
. be sampled inactive by the 82496 Cache Controller and MBC respectively.
KLOCK# activation is not qualified by the tag array look-up (hit/miss indications). As a result,
KLOCK# may be active before CADS# is asserted.
When Driven
LOCK#
KLOCK
CADS#
~
1''+-1
--+---Ir
COB97
Figure 5-26. KLOCK# to LOCK# Relationship
KLOCK# is asserted with CADS# for cycles in which LOCK# was asserted by the Pentium
processor with ADS#. KLOCK# de-assertion is a flow-through of one CLK from the CPU
LOCK# signal and occurs at least one CLK after the last CADS# in a LOCKed sequence.
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