Physical Cache; Memory Bus Width - Intel 82496 CACHE CONTROLLER User Manual

CACHE INITIALIZATION AND CONFIGURATION
Table 4-1. Pentium™ Processor Chip Set Initialization Recommendations
Cache BUSCHK# CLDRV
Cache Size Configurations @RESET @RESET
256K
1,2 HIGH HIGH
512K 3,4,5 LOW LOW
To simplify the configuration process, the Pentium processor BUSCHK# input path should be
designed such that a 0 ohm resistor connects the BUSCHK# pin to the inverse of RESET. The
resistor allows the system designer to change the polarity of BUSCHK# with minimal impact
to the system design. If the resistor is removed, this input is high due to the internal pullup
resistor. If the resistor is in the circuit, the input is low (inverse of the active RESET). Note
that the BUSCHK# input must meet all timings with respect to RESET as indicated in Figure
4-2 and in the text above.
The 82496 Cache Controller CLDRV signal shares a pin with the 82496 Cache Controller
BGT# signal. During reset, the CLDRV pin should be driven low or high as shown in Table 4-
7. During normal operation, this pin acts as the BGT# signal, and should be driven
accordingly.
4.2. PHYSICAL CACHE
The 82496 Cache Controller/82491 Cache SRAM's physical configurations consist of basic
architectural parameters determining line ratio, cache tagRAM size, lines per sector and bus
width. These parameters are sampled in the CLK prior to RESET sampled inactive and cannot
be dynamically changed. Table 4-2 shows the appropriate values of the configuration inputs,
CFG[2:0], for each possible cache configuration.
Table 4-2. 82496 Cache Controller/82491 Cache SRAM Configuration Inputs
Config No. Cache Size Line Ratio
Lines/sec
No. of Tags CFG2
CFG1 CFGO
1 256KB 1 1 8K 0 0 1
2 256KB 2 1 4K 1 1 1
3 512KB 1 2 8K 0 0 0
·4
512KB 2 1 8K 0 1 1
5
512KB
4 1
4K 1
1 0
4.2.1.
Memory Bus Width
The CPU-Cache Chip Set core supports 64- and 128-bit memory bus widths. Note that the
system designer can choose to implement a 32 bit memory bus (this is NOT a configuration
option).
4-4
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