Buschk - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.24.
BUSCHK#
BUSCHK# Bus Cycle Check
Indicates an unsuccessful completion of a bus cycle.
Input to Pentium processor (pin T03)
Synchronous to ClK
Signal Description
To configure the I/O buffers of the Pentium processor for use with the 82496 Cache
Controller/82491 Cache SRAM secondary cache as a chip set, BUSCHK# must be driven by
the MBC to the value shown in Table 4-1 (refer to section 4.1.1 at least 4 CPU clocks prior to
the falling edge of RESET.
To simplify the configuration process, the Pentium processor BUSCHK# input can be tied to
the inverse of RESET with a 0 ohm resistor in the path. The purpose of the resistor is to allow
changing the polarity with minimal impact ot the system design. If the resistor is removed, this
input is high due to the internal pullup resistor. If the resistor is in the circuit, the input is low
(inverse of the active RESET).
Refer to the Pentium™ Processor Data Book for a detailed description of this signal.
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