Cfa[6:0],Set[1 0:0],Tag[11 :0] - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.32.
CFA[6:0],SET[1 0:0],TAG[11 :0]
CFA[6:0], Configurable Address Pins
SET[10:0j, Contains the current physical address.
TAG[11:0j Input/Output between Pentium processor address pins and 82496 Cache
Controller (pins E15, F15, B17, C03, E07, C15, F16, B10, C10, E11, E10, E13,
D12, D13,C13,D15,D14,E14,D06,C02,B02,E08,B03, D08,C04,C05.B04.
E09. B05. D09)
Synchronous to ClK
Signal Description
These configurable address pins are connected to CPU address pins A[31:3]. The specific
address pin connections are configuration dependent. Refer to the Initialization and
Configuration chapter for additional details.
Refer to the Pentium™ Processor Data Book for a detailed description of the A[31:3] signals.
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