Intel 82496 CACHE CONTROLLER User Manual page 58

PINOUTS
Table 1-14.
Signal Interconnects
on Optimized Interface
Pentium™ Processor 82496 Cache Controller 82491 Cache SRAM
(1/0) 256KB: (1/0) 512KB: 256KB:
(1/0)
512KB:
VSS
--
-- AO
--
VSS
CFA5 CFA4 A1 AO
A[4:3] CFA[1 :0] CFA[1 :0] A[3:2]
A[2:1]
A5
CFA6 CFA5
A4
A3
A6 SETO CFA6 A5
A4
A[16:7] SET[10:1]
SET[9:0] A[15:6] A[14:5]
A17 TAGO SET10 A15
A[28:18]
TAG[11:1] TAG[10:0]
A29 CFA2 TAG 11
A30 CFA3
CFA2
A31 CFA4 CFA3
ADS# (0)
ADS# (I)
ADSC#(O) ADS# (I)
AHOLD (I) AHOLD (0)
AP
(1/0)
AP (110)
BE[7:0]# (0)
BE# (I), CDATA[7:4] (I) •
BLAST# (0) BLAST# (I)
BLEC# (0)
BLEC# (I)
BOFF# (I) BOFF# (0) BOFF#(I)
BRDYC# (I) BRDYC1#(0)
BRDYC2# (0) BRDYC# (I)
BT[3:0] (1/0) BT[3:0] (1/0)
BUS# (0) BUS# (I)
CACHE# (0) CACHE# (I)
D[63:0] (1/0) CDATA[7:0]
(1/0)
D/C# (0)
D/C# (I)
DP[7:0]
(1/0) CDATA[3:0]
(1/0) •
EADS# (I)
EADS# (0)
EWBE# (I) EWBE# (0)
I
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