Intel 82496 CACHE CONTROLLER User Manual page 301

HARDWARE INTERFACE
5.2.2.112. PCD
PCD Page Cacheability Disable
Indicates CPU cycle cacheability.
Output from Pentium processor (pin W04), Input to 82496 Cache Controller (pin
J16)
Synchronous to ClK
Signal Description
Refer to the Pentium™ Processor Data Book for a detailed description of this signal.
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