Snooping During Locked Cycles - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
SNPCLK must not be until after the falling edge of SNPCYC#. For
synchronous snoop mode, the second SNPSTB# sampled by CLK must not
be until the CLK following SNPCYC# active.
SNPSTB#
SNPCYC#
X
NEW SNPSTB# NOT ALLOWED
X
CDB4
Figure 5-15. New SNPSTB# Not Allowed
Locked cycles are used to guarantee an atomic Read-Modify-Write operation. The MBC must
not allow snoops between the BGT# of the fIrst Read portion of the locked sequence, and the
BGT# of the last Write portion. This is to ensure that the lock protocol is not violated. Section
5.1.2.5 describes the restriction which, if strictly met, will allow the system to snoop during
this portion of the locked sequence.
During read-for-ownership cycles, the MBC must not allow snoops between the BGT# of the
write-through and the BGT# of the allocation. This is to ensure that the snoop data is not stale.
Between the BGT# of the write-through and the BGT# of the allocation, the line is invalid in
the cache doing read-for-ownership (cache 1). Cache 2 (the cache from which data is being
transferred) has only a
partially
updated line. When the write-back is completed, the 64-bits of
recently modified data in cache 1 is surrounded by the modified data from cache 2. The
resulting
line is the most recently modified line. Note that the line in cache 2 is invalidated
before the cache-to-cache transfer. Also, once the transfer is complete, the line exists in cache
1 in the modified state.
5.1.2.5.
SNOOPING DURING LOCKED CYCLES
Locked cycles are used to guarantee atomic Read-Modify-Write operation. The system
assumes that a data item will not be accessed by another device until the read and write have
been completed. There is a situation using the 82496 Cache Controller/82491 Cache SRAM
where this lock protocol may be violated unless certain restrictions are met.
A snoop write-back cycle takes priority over all other cycles in the 82496 Cache Controller
cache controller. If the CPU is performing a Read-Modify-Write (Le., locked) cycle and the
data is Modified in the 82496 Cache Controller/82491 Cache SRAM, the data could be written
back on a snoop between the Read and Write parts'of the intended atomic cycle. This violates
the lock protocol and could cause unintended system operation.
To provide maximum performance in Pentium processor CPU-Cache Chip Set systems, the
82496 Cache Controller allows snooping during locked cycles, however, the following
condition must be met: the address being snooped must not be in the same cache line as that of
the locked operation.
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