Intel 82496 CACHE CONTROLLER User Manual page 278

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HARDWARE INTERFACE
5.2.2.94.
MHITM#
MHITM# Memory Snoop Hit 1M]
Indicates snoop hit to a modified line.
Output from 82496 Cache Controller (pin J05)
Synchronous to ClK
Signal Description
MHITM# is asserted by the 82496 Cache Controller to indicate a snoop hit to a line in [M]
state. Once a snoop hits a line in the [M] state, the 82496 Cache Controller automatically
schedules a snoop write-back. MHITM# is valid one CLK after SNPCYC# and remains valid
until the next snoop cycle. If MHITM# is active (LOW) in the CLK after SNPCYC#, it will
remain active until the CLK of CRDY# of the snoop write back.
If MHITM# is asserted by any cache during snooping, the bus master should back off from the
bus to allow a snoop write back.
When Driven
The snoop lookup is performed in the CLK in which SNPCYC# is asserted. MHITM# for the
snoop is driven on the next CLK and remains valid until SNPCYC# is asserted again.
MHlTM# is not valid in the CLK of SNPCYC#.
Relation to Other Signals
Pin Symbol Relation to Other Signals
BGT#
The 82496 Cache Controller ignores BGT# while both SNPBSY# and MHITM# are
active (i.e., during a snoop write back).
MTHIT# MTHIT# and MHITM# together indicate the results of an 82496 Cache Controller
snoop lookup.
CRDY#
MHITM# goes inactive on clock after CRDY# of a snoop write back cycle.
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